llvm dev - Feb 2012 - [LLVMdev] HELP - tblgen -gen-asm-matcher restrictions on .td content

I'm trying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp.

What added restrictions for the .td file contents are there for tblgen
-gen-asm-matcher?


For the Mips platform we create the following .inc files through tblgen.

tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter)
tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(MipsCommonTableGen)

When I started trying to generate MipsGenAsmMatcher.inc for the assembler I
started getting errors.

tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/  Mips.tdIncluded from
Mips.td:24:
MipsInstrInfo.td:833:14: error: Instruction 'LWL' has no tokens
defm LWL     : LoadUnAlign32<0x22>;

How does it get a token?

Commenting out this code I got farther and found that a register that didn't
have a formal def in MipsRegisterInfo.td would get flagged.

     !strconcat(instr_asm, "\t$$zero, $rs, $rt"),

% tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/  Mips.td
Included from Mips.td:24:
Included from MipsInstrInfo.td:1120:
Mips64InstrInfo.td:173:1: error: error: unable to find operand: 'zero'
def DSDIV    : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
^

Any information on this would be great.

Cheers,

Jack
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20120126/26783d6b/attachment.html>

Hi Jack,
On Jan 25, 2012, at 6:45 PM, "Carter, Jack" <jcarter at
mips.com> wrote:
> I'm trying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp. 
> 
> What added restrictions for the .td file contents are there for tblgen
-gen-asm-matcher?
> 
Lots, as you're finding, almost all of them completely undocumented. :(
> For the Mips platform we create the following .inc files through tblgen.
> 
> tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
> tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
> tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter)
> tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
> tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
> tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
> tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
> tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
> add_public_tablegen_target(MipsCommonTableGen)
> 
> When I started trying to generate MipsGenAsmMatcher.inc for the assembler I
started getting errors.
> 
> tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/  Mips.tdIncluded
from Mips.td:24:
> MipsInstrInfo.td:833:14: error: Instruction 'LWL' has no tokens
> defm LWL     : LoadUnAlign32<0x22>;
> 
> How does it get a token?
> 
>From the assembly string used by the instruction printer. That's saying
there's a variant in the multi class expansion that doesn't have a
string associated with it that can be used to derive the syntax.
> Commenting out this code I got farther and found that a register that
didn't have a formal def in MipsRegisterInfo.td would get flagged.
> 
>      !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
> 
> % tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/  Mips.td
> Included from Mips.td:24:
> Included from MipsInstrInfo.td:1120:
> Mips64InstrInfo.td:173:1: error: error: unable to find operand:
'zero'
> def DSDIV    : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
> ^
> 
That's a bug/limitation of the asm matcher. For something similar, see
X86InstrInfo.td's commented out definition of ShiftRotateByOneAlias.

-Jim
> Any information on this would be great.
> 
> Cheers,
> 
> Jack
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20120202/5bb6b2f2/attachment.html>

Once again, thank you.

I will add these explanations to my assembler journal and we may end up with
some documentation by the time I am done.

Jack

________________________________
From: Jim Grosbach [grosbach at apple.com]
Sent: Thursday, February 02, 2012 4:50 PM
To: Carter, Jack
Cc: List
Subject: Re: HELP - tblgen -gen-asm-matcher restrictions on .td content

Hi Jack,
On Jan 25, 2012, at 6:45 PM, "Carter, Jack" <jcarter at
mips.com<mailto:jcarter at mips.com>> wrote:

I'm trying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp.

What added restrictions for the .td file contents are there for tblgen
-gen-asm-matcher?


Lots, as you're finding, almost all of them completely undocumented. :(

For the Mips platform we create the following .inc files through tblgen.

tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter)
tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(MipsCommonTableGen)

When I started trying to generate MipsGenAsmMatcher.inc for the assembler I
started getting errors.

tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/  Mips.tdIncluded from
Mips.td:24:
MipsInstrInfo.td:833:14: error: Instruction 'LWL' has no tokens
defm LWL     : LoadUnAlign32<0x22>;

How does it get a token?

>From the assembly string used by the instruction printer. That's saying
there's a variant in the multi class expansion that doesn't have a
string associated with it that can be used to derive the syntax.
Commenting out this code I got farther and found that a register that didn't
have a formal def in MipsRegisterInfo.td would get flagged.

     !strconcat(instr_asm, "\t$$zero, $rs, $rt"),

% tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/  Mips.td
Included from Mips.td:24:
Included from MipsInstrInfo.td:1120:
Mips64InstrInfo.td:173:1: error: error: unable to find operand: 'zero'
def DSDIV    : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
^


That's a bug/limitation of the asm matcher. For something similar, see
X86InstrInfo.td's commented out definition of ShiftRotateByOneAlias.

-Jim

Any information on this would be great.

Cheers,

Jack

-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20120203/dd0a59ef/attachment.html>