search for: mipsgenasmmatch

I'm trying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp. What added restrictions for the .td file contents are there for tblgen -gen-asm-matcher? For the Mips platform we create the following .inc files through tblgen. tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info) tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-...

Hi Jack, On Jan 25, 2012, at 6:45 PM, "Carter, Jack" <jcarter at mips.com> wrote: > I'm trying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp. > > What added restrictions for the .td file contents are there for tblgen -gen-asm-matcher? > Lots, as you're finding, almost all of them completely undocumented. :( > For the Mips platform we create the following .inc files through tblgen. > &...

...MipsGenDAGISel.inc MipsGenCallingConv.inc \ - MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc \ + MipsGenSubtargetInfo.inc MipsGenFastISel.inc MipsGenMCCodeEmitter.inc \ MipsGenDisassemblerTables.inc \ MipsGenMCPseudoLowering.inc MipsGenAsmMatcher.inc I get an error. Included from /home/rkotler/workspace/llvm/lib/Target/Mips/MipsInstrInfo.td:1474: /home/rkotler/workspace/llvm/lib/Target/Mips/Mips64InstrInfo.td:89:1: error: Duplicate record in FastISel table! def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB, sub>,...

I believe that table gen builds MipsGenAsmMatcher.inc which has the Match routines like MatchRegisterName(). In building MipsGenAsmMatcher.inc I am hitting the following issue (actually several, but they may be related). It may have something to do with the $$ escape sequence: /home/jcarter/workarea/llvm/lib/Target/Mips/Mips64InstrInfo.td:173:...

On Jan 31, 2012, at 1:26 PM, Carter, Jack wrote: > I'm trying to build a standalone assembler for Mips using AsmParser. > > Following the lead of X86, ARM and MBlaze I have run tblgen -gen-asm-matcher on Mips.td to produce tables and methods to aid the parser (MipsAsmParser.cpp) which is a stripped down ARM implementation. > > I am getting an assertion for what I believe are

...30GenCallingConv.inc +MSP430GenDAGISel.inc +MSP430GenInstrInfo.inc +MSP430GenRegisterInfo.inc +MSP430GenSubtargetInfo.inc diff --git a/lib/Target/Mips/.gitignore b/lib/Target/Mips/.gitignore new file mode 100644 index 0000000..27c073c --- /dev/null +++ b/lib/Target/Mips/.gitignore @@ -0,0 +1,12 @@ +MipsGenAsmMatcher.inc +MipsGenAsmWriter.inc +MipsGenCallingConv.inc +MipsGenCodeEmitter.inc +MipsGenDAGISel.inc +MipsGenDisassemblerTables.inc +MipsGenEDInfo.inc +MipsGenInstrInfo.inc +MipsGenMCCodeEmitter.inc +MipsGenMCPseudoLowering.inc +MipsGenRegisterInfo.inc +MipsGenSubtargetInfo.inc diff --git a/lib/Target/N...

I'm trying to build a standalone assembler for Mips using AsmParser. Following the lead of X86, ARM and MBlaze I have run tblgen -gen-asm-matcher on Mips.td to produce tables and methods to aid the parser (MipsAsmParser.cpp) which is a stripped down ARM implementation. I am getting an assertion for what I believe are multiple register definitions with the same name. llvm-tblgen: