search for: mips64instrinfo

...el.inc MipsGenMCCodeEmitter.inc \ MipsGenDisassemblerTables.inc \ MipsGenMCPseudoLowering.inc MipsGenAsmMatcher.inc I get an error. Included from /home/rkotler/workspace/llvm/lib/Target/Mips/MipsInstrInfo.td:1474: /home/rkotler/workspace/llvm/lib/Target/Mips/Mips64InstrInfo.td:89:1: error: Duplicate record in FastISel table! def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB, sub>, ADD_FM<0, 0x2e>; ^ make[3]: *** [/home/rkotler/llvmw/build/lib/Target/Mips/Debug+Asserts/MipsGenFastISel.inc.tmp] Error 1 Then it creates a blank file for Mi...

...rther and found that a register that didn't have a formal def in MipsRegisterInfo.td would get flagged. !strconcat(instr_asm, "\t$$zero, $rs, $rt"), % tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/ Mips.td Included from Mips.td:24: Included from MipsInstrInfo.td:1120: Mips64InstrInfo.td:173:1: error: error: unable to find operand: 'zero' def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>; ^ Any information on this would be great. Cheers, Jack -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/...

...t didn't have a formal def in MipsRegisterInfo.td would get flagged. > > !strconcat(instr_asm, "\t$$zero, $rs, $rt"), > > % tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/ Mips.td > Included from Mips.td:24: > Included from MipsInstrInfo.td:1120: > Mips64InstrInfo.td:173:1: error: error: unable to find operand: 'zero' > def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>; > ^ > That's a bug/limitation of the asm matcher. For something similar, see X86InstrInfo.td's commented out definition of ShiftRotateByOneAlia...

...builds MipsGenAsmMatcher.inc which has the Match routines like MatchRegisterName(). In building MipsGenAsmMatcher.inc I am hitting the following issue (actually several, but they may be related). It may have something to do with the $$ escape sequence: /home/jcarter/workarea/llvm/lib/Target/Mips/Mips64InstrInfo.td:173:1: error: error: unable to find operand: 'zero' def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>; Here is the sequence of definitions: def SDT_MipsDivRem : SDTypeProfile<0, 2, [SDTCisInt<0>,...

On 4 October 2016 at 19:50, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > If there are no objections, I'd like to start working on this soon... > > For the AMDGPU target this implies that RC->getSize will no longer be > available in the MC layer. Another advantage of this work that hasn't been mentioned yet is it will reduce the number of uses