similar to: [LLVMdev] HELP - tblgen -gen-asm-matcher restrictions on .td content

Hi Jack, On Jan 25, 2012, at 6:45 PM, "Carter, Jack" <jcarter at mips.com> wrote: > I'm trying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp. > > What added restrictions for the .td file contents are there for tblgen -gen-asm-matcher? > Lots, as you're finding, almost all of them completely undocumented. :( > For the Mips platform we create

What is the purpose of tablegen created files for fast-isel? If I make the following change to Makefile in lib/Target/Mips BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \ MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \ MipsGenDAGISel.inc MipsGenCallingConv.inc \ - MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc \ +

I believe that table gen builds MipsGenAsmMatcher.inc which has the Match routines like MatchRegisterName(). In building MipsGenAsmMatcher.inc I am hitting the following issue (actually several, but they may be related). It may have something to do with the $$ escape sequence: /home/jcarter/workarea/llvm/lib/Target/Mips/Mips64InstrInfo.td:173:1: error: error: unable to find operand:

Add several .gitignore rules to various directories to ensure a clean worktree after a default build. Signed-off-by: Ramkumar Ramachandra <artagnon at gmail.com> --- Just cloned and built LLVM. This annoyed me. Here's a trivial patch. .gitignore | 10 ++++++++++ bindings/ocaml/llvm/.gitignore | 1 + docs/.gitignore

Hi, I am trying to minimize a rather complex function of 5 parameters with gafit and nlm. Besides some problems with both optimization algorithms (with respect to consistantly generating similar results), I tried to run this optimization about a hundred times for yet two other parameters. Unfortunately, as the log below shows, during that batch process R starts to eat up all my RAM,

Dear community, I have developed a backend of new 32-bit RISC ISA, which does not have unaligned memory access instructions (e.g., LWL, LWR, SWL, and SWR in MIPS). Since char and short variables are not 32-bit alignment, these variables cannot be correctly accessed. Therefore, alignment member functions, especially getCharAlign() and getShortAlign() of TargetInfo class in

Hi Jack, On Sat, Mar 2, 2013 at 8:15 AM, Jack Carter <Jack.Carter at imgtec.com> wrote: > Jia, > > I made what I believe to be the correct changes and rebuilt clang and llc. Are the results what you expected? I so I will prepare the patches for commitment. > > Jack > > clang ../mips_R_JiaLiu.c -o mips_R_JiaLiu.ll -emit-llvm -O3 -S -target mipsel-unknown-linux -std=gnu89

On 9/24/2016 7:20 AM, Alex Bradbury wrote: > My concern is that all of the above adds yet more complexity to what > is already (in my view) a fairly difficult part of LLVM to understand. > The definition of MyRegisterClass is not so bad though, and perhaps it > doesn't matter how it works under the hood to the average backend > writer. I agree with the complexity, but I would

On 5/1/2018 4:35 AM, Hiroyuki Chishiro via llvm-dev wrote: > Dear community, > > I have developed a backend of new 32-bit RISC ISA, which does not have > unaligned memory access instructions (e.g., LWL, LWR, SWL, and SWR in > MIPS). > Since char and short variables are not 32-bit alignment, these > variables cannot be correctly accessed. > Therefore, alignment member

Maybe try: .set noat AT is needed to create certain instructions from pseudo instructions, so you have to be careful how you use this. Some instructions that you can use in Mips assembler are in fact pseudos. While AT is not available to it (.set noat), the assembler can not assemble certain pseudos for you. On 03/03/2013 06:02 PM, Jia Liu wrote: > Hi Jack, > > On Sat, Mar 2, 2013

On Jan 31, 2012, at 1:26 PM, Carter, Jack wrote: > I'm trying to build a standalone assembler for Mips using AsmParser. > > Following the lead of X86, ARM and MBlaze I have run tblgen -gen-asm-matcher on Mips.td to produce tables and methods to aid the parser (MipsAsmParser.cpp) which is a stripped down ARM implementation. > > I am getting an assertion for what I believe are

So, having subscribed recently to the ruby-talk mailing list, I''ve noticed that wxruby doesn''t seem to have the "respect" of other GUI libraries. I know GUI-library preference is a holy war almost up there with vi versus emacs, but since I''m a wxruby developer, I''d like to know what people "don''t" like about wxruby. Otherwise,

- my old email address. The ISA_* classes might not be the best choice for this. There's an overall hierarchy and ordering to the ISA_* classes since they represent the generations of the MIPS ISA. If these extensions are available in Loongson chips based on MIPS32r1 and MIPS32r2 for example, it becomes difficult to describe with ISA_* classes without duplicating instruction definitions or

On Sat, May 7, 2011 at 12:33 PM, Eric Christopher <echristo at apple.com> wrote: > > On May 5, 2011, at 11:26 PM, Liu wrote: > >>  some some type errors in the commentary of *.td file. >> such as: >> lib/Target/Mips/MipsInstrFormats.td >> MipsRegisterInfo.td - Mips Register defs >> it should be >> MipsInstrFormats.td - Mips Instruction Formats

On May 7, 2011, at 2:47 AM, Liu wrote: > On Sat, May 7, 2011 at 12:33 PM, Eric Christopher <echristo at apple.com> wrote: >> >> On May 5, 2011, at 11:26 PM, Liu wrote: >> >>> some some type errors in the commentary of *.td file. >>> such as: >>> lib/Target/Mips/MipsInstrFormats.td >>> MipsRegisterInfo.td - Mips Register defs

Hi all, I find some some type errors in the commentary of *.td file. such as: lib/Target/Mips/MipsInstrFormats.td MipsRegisterInfo.td - Mips Register defs it should be MipsInstrFormats.td - Mips Instruction Formats lib/Target/Mips/MipsInstrInfo.td MipsInstrInfo.td - Mips Register defs it should be MipsInstrInfo.td - Target Description for Mips Target and some thing I think it is wrong in

On May 5, 2011, at 11:26 PM, Liu wrote: > some some type errors in the commentary of *.td file. > such as: > lib/Target/Mips/MipsInstrFormats.td > MipsRegisterInfo.td - Mips Register defs > it should be > MipsInstrFormats.td - Mips Instruction Formats > > lib/Target/Mips/MipsInstrInfo.td > MipsInstrInfo.td - Mips Register defs > it should be > MipsInstrInfo.td -

I am considering using MipsInstPrinter::printAliasInstr, which is auto-generated in MipsGenAsmWriter.inc, to print assembly idioms defined as instruction aliases. For example, an instruction which used to be printed as "nor $1, $2, $zero" can be printed as "not $1, $2" This is nice because it makes the code printed by code-gen or disassembler more readable. However, the

File: trunk/llvm/lib/Target/Hexagon/CMakeLists.txt set(LLVM_TARGET_DEFINITIONS Hexagon.td) tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info) tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info) tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel) tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv) tablegen(LLVM

Hi all, I find clang-mips doesn't support constraint 'R' and I'm trying make LLVM/Clang support it. I did a little job, but Clang can not generate right code, it use the same register in inline asm, and the binary will segment fault in MIPS environment. My test case: /* constraint.c */ #include <stdio.h> int main(int argc, char* argv[]) { int a = 4; int b = 10;