Displaying 6 results from an estimated 6 matches for "mipsgendagisel".
2014 Apr 24
3
[LLVMdev] tablegen for fast isel
What is the purpose of tablegen created files for fast-isel?
If I make the following change to Makefile in lib/Target/Mips
BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \
MipsGenDAGISel.inc MipsGenCallingConv.inc \
- MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc \
+ MipsGenSubtargetInfo.inc MipsGenFastISel.inc
MipsGenMCCodeEmitter.inc \
MipsGenDisassemblerTables.inc \
MipsGenMCPseudoLowering.inc MipsGenAsmMatche...
2012 Jan 26
2
[LLVMdev] HELP - tblgen -gen-asm-matcher restrictions on .td content
...blgen.
tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter)
tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(MipsCommonTableGen)
When I started trying to generate MipsGenAsmMatcher.inc for the assembler I started getting errors.
tblgen -gen-asm-match...
2012 Feb 03
0
[LLVMdev] HELP - tblgen -gen-asm-matcher restrictions on .td content
...sGenRegisterInfo.inc -gen-register-info)
> tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
> tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter)
> tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
> tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
> tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
> tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
> tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
> add_public_tablegen_target(MipsCommonTableGen)
>
> When I started trying to generate MipsGenAsmMatcher.inc for the assembler I started getting error...
2016 Sep 24
2
RFC: Implement variable-sized register classes
On 9/24/2016 7:20 AM, Alex Bradbury wrote:
> My concern is that all of the above adds yet more complexity to what
> is already (in my view) a fairly difficult part of LLVM to understand.
> The definition of MyRegisterClass is not so bad though, and perhaps it
> doesn't matter how it works under the hood to the average backend
> writer.
I agree with the complexity, but I would
2012 Nov 13
2
[LLVMdev] [PATCH] .gitignore: add rules for a clean worktree
...+MSP430GenSubtargetInfo.inc
diff --git a/lib/Target/Mips/.gitignore b/lib/Target/Mips/.gitignore
new file mode 100644
index 0000000..27c073c
--- /dev/null
+++ b/lib/Target/Mips/.gitignore
@@ -0,0 +1,12 @@
+MipsGenAsmMatcher.inc
+MipsGenAsmWriter.inc
+MipsGenCallingConv.inc
+MipsGenCodeEmitter.inc
+MipsGenDAGISel.inc
+MipsGenDisassemblerTables.inc
+MipsGenEDInfo.inc
+MipsGenInstrInfo.inc
+MipsGenMCCodeEmitter.inc
+MipsGenMCPseudoLowering.inc
+MipsGenRegisterInfo.inc
+MipsGenSubtargetInfo.inc
diff --git a/lib/Target/NVPTX/.gitignore b/lib/Target/NVPTX/.gitignore
new file mode 100644
index 0000000..74001d1
--...
2018 Sep 06
2
How to add Loongson ISA for Mips target?
- my old email address.
The ISA_* classes might not be the best choice for this. There's an overall hierarchy and ordering to the ISA_* classes since they represent the generations of the MIPS ISA. If these extensions are available in Loongson chips based on MIPS32r1 and MIPS32r2 for example, it becomes difficult to describe with ISA_* classes without duplicating instruction definitions or