Displaying 6 results from an estimated 6 matches for "mipsgeninstrinfo".
2014 Apr 24
3
[LLVMdev] tablegen for fast isel
What is the purpose of tablegen created files for fast-isel?
If I make the following change to Makefile in lib/Target/Mips
BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \
MipsGenDAGISel.inc MipsGenCallingConv.inc \
- MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc \
+ MipsGenSubtargetInfo.inc MipsGenFastISel.inc
MipsGenMCCodeEmitter.inc \...
2012 Jan 26
2
[LLVMdev] HELP - tblgen -gen-asm-matcher restrictions on .td content
...ying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp.
What added restrictions for the .td file contents are there for tblgen -gen-asm-matcher?
For the Mips platform we create the following .inc files through tblgen.
tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter)
tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
tablege...
2012 Feb 03
0
[LLVMdev] HELP - tblgen -gen-asm-matcher restrictions on .td content
...e contents are there for tblgen -gen-asm-matcher?
>
Lots, as you're finding, almost all of them completely undocumented. :(
> For the Mips platform we create the following .inc files through tblgen.
>
> tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
> tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
> tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter)
> tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
> tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
> tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
> tablegen(LLVM MipsGenCallingConv.inc...
2015 Nov 23
3
Qs about TwoOperandAliasConstraint and TIED_TO
in llvm-3.6.2.src
1. when I put this around one of my instruction definitions in my target "InstrInfo.td" file,
let TwoOperandAliasConstraint = "$dst = $rs1" in {
}
I do not see any TIED_TO in the generated GenInstrInfo.inc file for the OperandInfo used by the instruction,
the question is what am I doing wrong ?
2. I've noticed that TwoOperandAliasConstraint
2016 Sep 24
2
RFC: Implement variable-sized register classes
On 9/24/2016 7:20 AM, Alex Bradbury wrote:
> My concern is that all of the above adds yet more complexity to what
> is already (in my view) a fairly difficult part of LLVM to understand.
> The definition of MyRegisterClass is not so bad though, and perhaps it
> doesn't matter how it works under the hood to the average backend
> writer.
I agree with the complexity, but I would
2012 Nov 13
2
[LLVMdev] [PATCH] .gitignore: add rules for a clean worktree
.../lib/Target/Mips/.gitignore
new file mode 100644
index 0000000..27c073c
--- /dev/null
+++ b/lib/Target/Mips/.gitignore
@@ -0,0 +1,12 @@
+MipsGenAsmMatcher.inc
+MipsGenAsmWriter.inc
+MipsGenCallingConv.inc
+MipsGenCodeEmitter.inc
+MipsGenDAGISel.inc
+MipsGenDisassemblerTables.inc
+MipsGenEDInfo.inc
+MipsGenInstrInfo.inc
+MipsGenMCCodeEmitter.inc
+MipsGenMCPseudoLowering.inc
+MipsGenRegisterInfo.inc
+MipsGenSubtargetInfo.inc
diff --git a/lib/Target/NVPTX/.gitignore b/lib/Target/NVPTX/.gitignore
new file mode 100644
index 0000000..74001d1
--- /dev/null
+++ b/lib/Target/NVPTX/.gitignore
@@ -0,0 +1,5 @@
+NVPTXGenA...