Displaying 6 results from an estimated 6 matches for "ddiv".
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2006 Oct 31
0
6370694 ddivs dmae tests cause ASSERT panics on x86.
Author: cth
Repository: /hg/zfs-crypto/gate
Revision: cf0073e46b66d789d019f968fd5bf535cc7110bb
Log message:
6370694 ddivs dmae tests cause ASSERT panics on x86.
Files:
update: usr/src/uts/i86pc/io/rootnex.c
update: usr/src/uts/i86pc/os/ddi_impl.c
2012 Jan 26
2
[LLVMdev] HELP - tblgen -gen-asm-matcher restrictions on .td content
...str_asm, "\t$$zero, $rs, $rt"),
% tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/ Mips.td
Included from Mips.td:24:
Included from MipsInstrInfo.td:1120:
Mips64InstrInfo.td:173:1: error: error: unable to find operand: 'zero'
def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
^
Any information on this would be great.
Cheers,
Jack
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2012 Feb 03
0
[LLVMdev] HELP - tblgen -gen-asm-matcher restrictions on .td content
...$rt"),
>
> % tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/ Mips.td
> Included from Mips.td:24:
> Included from MipsInstrInfo.td:1120:
> Mips64InstrInfo.td:173:1: error: error: unable to find operand: 'zero'
> def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
> ^
>
That's a bug/limitation of the asm matcher. For something similar, see X86InstrInfo.td's commented out definition of ShiftRotateByOneAlias.
-Jim
> Any information on this would be great.
>
> Cheers,
>
> Jack
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2018 Sep 07
4
Clang for the PlayStation 2
On Fri, 7 Sep 2018 at 17:48, Tim Northover <t.p.northover at gmail.com> wrote:
> I looked at your diffs and you've only changed one of the functions to
> return SDValue(), you need to change lowerFP_TO_SINT itself too. The
> one with the store is just there as an optimization; if it doesn't
> trigger (because of your diff) then lowerFP_TO_SINT will still create
> a
2012 Jan 19
0
[LLVMdev] Problem generating <target>GenAsmMatcher.inc
...tting the following issue (actually several, but they may be related). It may have something to do with the $$ escape sequence:
/home/jcarter/workarea/llvm/lib/Target/Mips/Mips64InstrInfo.td:173:1: error: error: unable to find operand: 'zero'
def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
Here is the sequence of definitions:
def SDT_MipsDivRem : SDTypeProfile<0, 2,
[SDTCisInt<0>,
SDTCisSameAs<0, 1>]>;
def MipsDivRem : SDNode<"MipsISD::DivRem&quo...
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++-
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index dfb093c..e38a3b8 100644
---