search for: mipsinstrinfo

...rote: > >>  some some type errors in the commentary of *.td file. >> such as: >> lib/Target/Mips/MipsInstrFormats.td >> MipsRegisterInfo.td - Mips Register defs >> it should be >> MipsInstrFormats.td - Mips Instruction Formats >> >> lib/Target/Mips/MipsInstrInfo.td >> MipsInstrInfo.td - Mips Register defs >> it should be >> MipsInstrInfo.td - Target Description for Mips Target >> >> and some thing I think it is wrong in lib/Target/Mips/MipsInstrFPU.td. >> >> Will the patch be OK? >> >> Best regards. &gt...

...e type errors in the commentary of *.td file. >>> such as: >>> lib/Target/Mips/MipsInstrFormats.td >>> MipsRegisterInfo.td - Mips Register defs >>> it should be >>> MipsInstrFormats.td - Mips Instruction Formats >>> >>> lib/Target/Mips/MipsInstrInfo.td >>> MipsInstrInfo.td - Mips Register defs >>> it should be >>> MipsInstrInfo.td - Target Description for Mips Target >>> >>> and some thing I think it is wrong in lib/Target/Mips/MipsInstrFPU.td. >>> >>> Will the patch be OK? >&...

Hi all, I find some some type errors in the commentary of *.td file. such as: lib/Target/Mips/MipsInstrFormats.td MipsRegisterInfo.td - Mips Register defs it should be MipsInstrFormats.td - Mips Instruction Formats lib/Target/Mips/MipsInstrInfo.td MipsInstrInfo.td - Mips Register defs it should be MipsInstrInfo.td - Target Description for Mips Target and some thing I think it is wrong in lib/Target/Mips/MipsInstrFPU.td. Will the patch be OK? Best regards. --Liu -------------- next part -------------- A non-text attachment was scrubbed...

On May 5, 2011, at 11:26 PM, Liu wrote: > some some type errors in the commentary of *.td file. > such as: > lib/Target/Mips/MipsInstrFormats.td > MipsRegisterInfo.td - Mips Register defs > it should be > MipsInstrFormats.td - Mips Instruction Formats > > lib/Target/Mips/MipsInstrInfo.td > MipsInstrInfo.td - Mips Register defs > it should be > MipsInstrInfo.td - Target Description for Mips Target > > and some thing I think it is wrong in lib/Target/Mips/MipsInstrFPU.td. > > Will the patch be OK? > > Best regards. > > --Liu > <Mips-td-co...

...conv) tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget) add_public_tablegen_target(MipsCommonTableGen) When I started trying to generate MipsGenAsmMatcher.inc for the assembler I started getting errors. tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/ Mips.tdIncluded from Mips.td:24: MipsInstrInfo.td:833:14: error: Instruction 'LWL' has no tokens defm LWL : LoadUnAlign32<0x22>; How does it get a token? Commenting out this code I got farther and found that a register that didn't have a formal def in MipsRegisterInfo.td would get flagged. !strconcat(instr_asm, &qu...

...targetInfo.inc -gen-subtarget) > add_public_tablegen_target(MipsCommonTableGen) > > When I started trying to generate MipsGenAsmMatcher.inc for the assembler I started getting errors. > > tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/ Mips.tdIncluded from Mips.td:24: > MipsInstrInfo.td:833:14: error: Instruction 'LWL' has no tokens > defm LWL : LoadUnAlign32<0x22>; > > How does it get a token? > >From the assembly string used by the instruction printer. That's saying there's a variant in the multi class expansion that doesn't hav...

...rd). There I do BuildMI (newOpcode) and followed by >> br2uncond->eraseFromParent(). This results in br1cond loosing it's >> label/offset. How could I resolve this? >Your code is broken. AnalyzeBranch should not modify anything. > > > >I was taking a clue from Mips/MipsInstrInfo.cpp: AnalyzeBranch :( >Could you please suggest appropriate alternative place for such a modification? >Best regards, > >Girish. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120124/0e1db35d/att...

...Emitter.inc \ + MipsGenSubtargetInfo.inc MipsGenFastISel.inc MipsGenMCCodeEmitter.inc \ MipsGenDisassemblerTables.inc \ MipsGenMCPseudoLowering.inc MipsGenAsmMatcher.inc I get an error. Included from /home/rkotler/workspace/llvm/lib/Target/Mips/MipsInstrInfo.td:1474: /home/rkotler/workspace/llvm/lib/Target/Mips/Mips64InstrInfo.td:89:1: error: Duplicate record in FastISel table! def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB, sub>, ADD_FM<0, 0x2e>; ^ make[3]: *** [/home/rkotler/llvmw/build/lib/Target/Mips/Debug+Asserts/M...

...false; + return false; } diff --git a/lib/Target/Mips/MipsLongBranch.cpp b/lib/Target/Mips/MipsLongBranch.cpp index 2efe534..bf5ad37 100644 --- a/lib/Target/Mips/MipsLongBranch.cpp +++ b/lib/Target/Mips/MipsLongBranch.cpp @@ -399,6 +399,8 @@ static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) { } bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) { + if (TM.getSubtarget<MipsSubtarget>().inMips16Mode()) + return false; if ((TM.getRelocationModel() == Reloc::PIC_) && TM.getSubtarget<MipsSubtarget>().isABI_O32() && F...

On Thu, Mar 28, 2013 at 12:22 PM, Nadav Rotem <nrotem at apple.com> wrote: > IMHO the right way to handle target function attributes is to > re-initialize the target machine and TTI for every function (if the > attributes changed). Do you have another solution in mind ? I don't really understand this. TargetMachine and TTI may be quite expensive to initialize. Doing so for

>> br2uncond->eraseFromParent(). This results in br1cond loosing it's >> label/offset. How could I resolve this? > Your code is broken. AnalyzeBranch should not modify anything. > > I was taking a clue from Mips/MipsInstrInfo.cpp: AnalyzeBranch :( > Could you please suggest appropriate alternative place for such a > modification? Ah sorry, my memory served me wrong. You can modify the stuff there, but very careful :) It's hard to tell w/o seeing the actual code. But I don't see how inserting new instructio...

Hi LLVM developers, GCC[1] is able to use Loongson ISA[2] for instruction selection: $ cat hello.c #include <stdio.h> int main(int argc, char *argv[]) { printf("Hello World\n"); return 0; } $ gcc -O0 -S hello.c $ cat hello.s .file 1 "hello.c" .section .mdebug.abi64 .previous .nan legacy .gnu_attribute 4, 1 .abicalls

Hello David, Thanks for your example. Is that means that DAG pattern is consist of LLVM IR instruction?? I met an example [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] of MipsInstrInfo.td, but I can't find correspond LLVM IR instruction of "set" in "LLVM Language Reference Manual". Is that correspond to $dst = op $b, $c?? Would you mind to tell me whether there is a reference of all possible element of DAG?? thanks a lot yi-hong 2011/1/25 David A. Green...

Sorry, I meant to say, I added code to prevent llc from running machine verifier after delay slots are filled. MipsInstrInfo::AnalyzeBranch generates incorrect results after delay slots are filled. Also, it seems that code in MachineVerifier.cpp wasn't written with architectures that have delay slots in mind. On Wed, Apr 25, 2012 at 11:59 AM, Akira Hatanaka <ahatanak at gmail.com> wrote: > Hi Anton, > &...

Hi Anton, I ran llc with -verify-coalescing. There were no error messages. Then I added code in MipsPassConfig::addPreEmitPass() to prevent machine verifier from running post delay -slot-filler, and ran llc again. Again, there were no error messages. This is the list of passes run after post-RA scheduling. machine verifier is run twice after post RA scheduler (and CriticalAntiDepBreaker) is run.

Hi Kevin, To get some portion of a constant immediate you can use SDNodeXForms to transform constant SDNodes into other values. For a worked example, in the MIPS backend we use this for constant synthesis by materializing the value into a register: (From lib/Target/MipsInstrInfo.td): // Transformation Function - get the lower 16 bits. def LO16 : SDNodeXForm<imm, [{ return getImm(N, N->getZExtValue() & 0xFFFF); }]>; The above fragment will take an immediate node and get the lower 16 bits. // Transformation Function - get the higher 16 bits. def HI16 : SDN...

Hi all, This seems like a dumb question but while setting up a pattern in TD file, I got stuck on trying to get each half of an immediate as the half-sized type (ie. i64 imm -> pair of i32 imm's). Is there an existing way to do it? I've tried the 'EXTRACT_SUBREG' but that seems to error at the end of scheduling. Looking at Target.td, I'm not sure which opcode is meant

...lvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > LLVM MIPS backend now supports different MIPS ISA like mips1, mips2, > mips3, mips32, mips32r6 etc. If Loongson ISA just add a few new > instructions I think you do not have to add a new subtarget. Take a > look at MipsInstrInfo.td file. In that file there are multiple > ISA_MIPSxxx classes. Take for example ISA_MIPS3 and search it through > *.td files. Here is an example of instruction definition specific to > mips3: > [[ > def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, >...

...ing or maybe even integer multiply if you don't implement that. In some cases, the original instruction may be directly emitted by the compiler, outside of the framework td files. Then you'll have to modify c++ code and emit an alternate sequence. Here are some simple patterns from the MipsInstrInfo.td //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// // Small immediates def : MipsPat<(i32 immSExt16:$in),...

Thanks for your reply. We are trying to implement a simple Mips-based CPU with just for teaching purpose, so we delete some instructions which are not commonly used, thus the task won't be too hard for students. I am responsible for modifying the compiler so that the compiler won't emit unsupported instructions. In order to avoid "can not select" error, I am trying to expand