Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp. The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues. This can be reproduced by setting in any target: setOperationAction(ISD::AND, MVT::i8, Promote); setOperationAction(ISD::AND, MVT::v2i8, Promote); setOperationAction(ISD::AND, MVT::i16, Promote); Let me know if this is good, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120727/5e20d318/attachment.html> -------------- next part -------------- A non-text attachment was scrubbed... Name: codegen_new_vec1_types.patch Type: application/octet-stream Size: 10556 bytes Desc: codegen_new_vec1_types.patch URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120727/5e20d318/attachment.obj>
I think that you attached the wrong patch. The attached patch is the one which adds the new MVT types. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah Sent: Saturday, July 28, 2012 01:54 To: Developers Mailing List Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]> Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp. The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues. This can be reproduced by setting in any target: setOperationAction(ISD::AND, MVT::i8, Promote); setOperationAction(ISD::AND, MVT::v2i8, Promote); setOperationAction(ISD::AND, MVT::i16, Promote); Let me know if this is good, Micah --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120728/7eddbc86/attachment.html>
No, that is correct. I am adding the new types so that I can bitcast v2i8 into a v1i16 and then perform the 'and' operation and have legalize types turn the v1i16 into a scalar. Though I am having trouble in understanding how x86 supports the <1 x i64> type. Based on looking at the code, it should fail because v1i64 is not supported on the x86 platform as far as I can tell. Micah From: Rotem, Nadav [mailto:nadav.rotem at intel.com] Sent: Saturday, July 28, 2012 12:56 PM To: Villmow, Micah; Developers Mailing List Subject: RE: Vector promotion broken for <2 x [i8|i16]> I think that you attached the wrong patch. The attached patch is the one which adds the new MVT types. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah Sent: Saturday, July 28, 2012 01:54 To: Developers Mailing List Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]> Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp. The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues. This can be reproduced by setting in any target: setOperationAction(ISD::AND, MVT::i8, Promote); setOperationAction(ISD::AND, MVT::v2i8, Promote); setOperationAction(ISD::AND, MVT::i16, Promote); Let me know if this is good, Micah --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120730/4f269539/attachment.html>
Micah, I think that your patch is missing the necessary modifications in lib/VMCore/ValueTypes.cpp to EVT::getEVTString() and EVT::getTypeForEVT. -Hal On Fri, 27 Jul 2012 22:54:24 +0000 "Villmow, Micah" <Micah.Villmow at amd.com> wrote:> Vector promotion which is new in LLVM 3.1 is broken for sub32 bit > types. The problem is in the VectorLegalizer::PromoteVectorOp. The > function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, > <2 x i16> or <4 x i8>. The problem is that there are no vectors of > size 1 defined for i32 or i16. The attached patch fixes these issues. > > This can be reproduced by setting in any target: > setOperationAction(ISD::AND, MVT::i8, Promote); > setOperationAction(ISD::AND, MVT::v2i8, Promote); > setOperationAction(ISD::AND, MVT::i16, Promote); > > Let me know if this is good, > Micah >-- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory
Ahh yep, thanks for catching that, new patch attached.> -----Original Message----- > From: Hal Finkel [mailto:hfinkel at anl.gov] > Sent: Tuesday, July 31, 2012 1:40 PM > To: Villmow, Micah > Cc: Developers Mailing List > Subject: Re: [LLVMdev] Vector promotion broken for <2 x [i8|i16]> > > Micah, > > I think that your patch is missing the necessary modifications in > lib/VMCore/ValueTypes.cpp to EVT::getEVTString() and EVT::getTypeForEVT. > > -Hal > > On Fri, 27 Jul 2012 22:54:24 +0000 > "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > > > Vector promotion which is new in LLVM 3.1 is broken for sub32 bit > > types. The problem is in the VectorLegalizer::PromoteVectorOp. The > > function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, > > <2 x i16> or <4 x i8>. The problem is that there are no vectors of > > size 1 defined for i32 or i16. The attached patch fixes these issues. > > > > This can be reproduced by setting in any target: > > setOperationAction(ISD::AND, MVT::i8, Promote); > > setOperationAction(ISD::AND, MVT::v2i8, Promote); > > setOperationAction(ISD::AND, MVT::i16, Promote); > > > > Let me know if this is good, > > Micah > > > > > > -- > Hal Finkel > Postdoctoral Appointee > Leadership Computing Facility > Argonne National Laboratory-------------- next part -------------- A non-text attachment was scrubbed... Name: codegen_new_vec1_types.patch Type: application/octet-stream Size: 11997 bytes Desc: codegen_new_vec1_types.patch URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120731/1492dd3a/attachment.obj>
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