search for: sub32

...C, spx_word16_t *g, spx_word16_t pitch_control) { spx_word32_t sum = 0; sum = ADD32(sum,MULT16_16(MULT16_16_16(g[0],pitch_control),C[0])); sum = ADD32(sum,MULT16_16(MULT16_16_16(g[1],pitch_control),C[1])); sum = ADD32(sum,MULT16_16(MULT16_16_16(g[2],pitch_control),C[2])); sum = SUB32(sum,MULT16_16(MULT16_16_16(g[0],g[1]),C[3])); sum = SUB32(sum,MULT16_16(MULT16_16_16(g[2],g[1]),C[4])); sum = SUB32(sum,MULT16_16(MULT16_16_16(g[2],g[0]),C[5])); sum = SUB32(sum,MULT16_16(MULT16_16_16(g[0],g[0]),C[6])); sum = SUB32(sum,MULT16_16(MULT16_16_16(g[1],g[1]),C[7])); s...

...e obtained the follow error: "Error: Can not represent OFFSET_IMM8 relocation in this object file format (1)" I have defined FIXED_POINT 1 and ARM4_ASM. The error is in the function forced_pitch_quant contained in ltp.c. The line that produce the error is: target[i]=EXTRACT16(SATURATE(SUB32(EXTEND32(target[i]),EXTEND32(res[i])),32700)); Why this error??? In the emulator i have no problem. I resolved with the sequent workaround: spx_word16_t tmp = EXTRACT16(SATURATE(SUB32(EXTEND32(target[i]),EXTEND32(res[i])), 32700)); target[i] = tmp; Now i can compile e linking the lib in my appl...

Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp. The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues....

...difications in > lib/VMCore/ValueTypes.cpp to EVT::getEVTString() and EVT::getTypeForEVT. > > -Hal > > On Fri, 27 Jul 2012 22:54:24 +0000 > "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > > > Vector promotion which is new in LLVM 3.1 is broken for sub32 bit > > types. The problem is in the VectorLegalizer::PromoteVectorOp. The > > function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, > > <2 x i16> or <4 x i8>. The problem is that there are no vectors of > > size 1 defined for i32 or i16...

...to EVT::getEVTString() and > > EVT::getTypeForEVT. > > > > -Hal > > > > On Fri, 27 Jul 2012 22:54:24 +0000 > > "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > > > > > Vector promotion which is new in LLVM 3.1 is broken for sub32 bit > > > types. The problem is in the VectorLegalizer::PromoteVectorOp. The > > > function getTypeToPromoteTo will return a <2 x i32> for a <2 x > > > i8>, <2 x i16> or <4 x i8>. The problem is that there are no > > > i8>vectors of &gt...

...t your patch is missing the necessary modifications in lib/VMCore/ValueTypes.cpp to EVT::getEVTString() and EVT::getTypeForEVT. -Hal On Fri, 27 Jul 2012 22:54:24 +0000 "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > Vector promotion which is new in LLVM 3.1 is broken for sub32 bit > types. The problem is in the VectorLegalizer::PromoteVectorOp. The > function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, > <2 x i16> or <4 x i8>. The problem is that there are no vectors of > size 1 defined for i32 or i16. The attached patch...

...s. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah Sent: Saturday, July 28, 2012 01:54 To: Developers Mailing List Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]> Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp. The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues....

...s. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah Sent: Saturday, July 28, 2012 01:54 To: Developers Mailing List Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]> Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp. The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues....

Hi Susan, With your bitcode file I am now able to reproduce the issue you're seeing. It looks like this is a problem with the naive rewriting from virtregs to physregs. It appears that the subreg field of physreg operands is ignored post-register allocation. In your testcase %vreg11:sub32 is being rewritten to RBX:sub32, but the :sub32 part is being quietly dropped when the assembly is written out. If this is expected behaviour, and is still happening in the development branch, then I'll add some sort of verification to catch it. The VirtRegMap::rewrite() method sidesteps this...

...ementptr inbounds %struct.float2* %x, i64 0, i32 0 %13 = load float* %x26, align 4 %14 = tail call float @llvm.nvvm.mul.rn.f(float %13, float %3) nounwind %add = fadd float %12, %14 %add29 = fadd float %10, %add %15 = tail call float @llvm.nvvm.add.rn.f(float %6, float %add29) nounwind %sub32 = fsub float %6, %15 %16 = tail call float @llvm.nvvm.add.rn.f(float %sub32, float %add29) nounwind %agg.result.0 = getelementptr inbounds %struct.float2* %agg.result, i64 0, i32 0 store float %16, float* %agg.result.0, align 8 %agg.result.1 = getelementptr inbounds %struct.float2* %agg.res...

...; With your bitcode file I am now able to reproduce the issue you're > seeing. It looks like this is a problem with the naive rewriting from > virtregs to physregs. It appears that the subreg field of physreg > operands is ignored post-register allocation. In your testcase > %vreg11:sub32 is being rewritten to RBX:sub32, but the :sub32 part is > being quietly dropped when the assembly is written out. If this is > expected behaviour, and is still happening in the development branch, > then I'll add some sort of verification to catch it. > > The VirtRegMap::rewrite(...

...ode file I am now able to reproduce the issue you're >> seeing. It looks like this is a problem with the naive rewriting from >> virtregs to physregs. It appears that the subreg field of physreg >> operands is ignored post-register allocation. In your testcase >> %vreg11:sub32 is being rewritten to RBX:sub32, but the :sub32 part is >> being quietly dropped when the assembly is written out. If this is >> expected behaviour, and is still happening in the development branch, >> then I'll add some sort of verification to catch it. >> >> The...

.... From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah Sent: Saturday, July 28, 2012 01:54 To: Developers Mailing List Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]> Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp. The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues....

My tst.bc is attached. I had to use ssh to copy it from my office machine to my home laptop. In case that corrupts it, I also put a copy here: http://pages.cs.wisc.edu/~horwitz/LANG/tst.bc I created the file like this: clang -emit-llvm -O0 -c tst.c -o tst.bc opt -mem2reg tst.bc > tst.mem2reg mv tst.mem2reg tst.bc Susan On 11/4/2012 3:27 PM, Lang Hames wrote: > Hi Susan, >

...uce the issue you're >>>> seeing. It looks like this is a problem with the naive rewriting from >>>> virtregs to physregs. It appears that the subreg field of physreg >>>> operands is ignored post-register allocation. In your testcase >>>> %vreg11:sub32 is being rewritten to RBX:sub32, but the :sub32 part is >>>> being quietly dropped when the assembly is written out. If this is >>>> expected behaviour, and is still happening in the development branch, >>>> then I'll add some sort of verification to catch it...

Hi, I just started with R and I found that there are many options to rearrange the data to do mixed models. I want to use the reshape function. I have 2 between subject variables and one within. I was able to change the data structure but still - the result of the aov functions are calculating everything as a within subject. the table looks like this: SerialNo breed treatment distance_1

...w able to reproduce the issue you're >>> seeing. It looks like this is a problem with the naive rewriting from >>> virtregs to physregs. It appears that the subreg field of physreg >>> operands is ignored post-register allocation. In your testcase >>> %vreg11:sub32 is being rewritten to RBX:sub32, but the :sub32 part is >>> being quietly dropped when the assembly is written out. If this is >>> expected behaviour, and is still happening in the development branch, >>> then I'll add some sort of verification to catch it. >>&g...

...cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Villmow, Micah > Sent: Saturday, July 28, 2012 01:54 > To: Developers Mailing List > Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]> > > Vector promotion which is new in LLVM 3.1 is broken for sub32 bit > types. The problem is in the VectorLegalizer::PromoteVectorOp. > The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, > <2 x i16> or <4 x i8>. The problem is that there are no vectors of size > 1 defined for i32 or i16. The attached patch...

...naive rewriting from >> virtregs to physregs. It appears that the subreg >> field of physreg >> operands is ignored post-register allocation. In your >> testcase >> %vreg11:sub32 is being rewritten to RBX:sub32, but >> the :sub32 part is >> being quietly dropped when the assembly is written >> out. If this is >> expected behaviour, and is still happening in the >> d...

...t2* %x, i64 0, i32 0 > %13 = load float* %x26, align 4 > %14 = tail call float @llvm.nvvm.mul.rn.f(float %13, float %3) nounwind > %add = fadd float %12, %14 > %add29 = fadd float %10, %add > %15 = tail call float @llvm.nvvm.add.rn.f(float %6, float %add29) nounwind > %sub32 = fsub float %6, %15 > %16 = tail call float @llvm.nvvm.add.rn.f(float %sub32, float %add29) > nounwind > %agg.result.0 = getelementptr inbounds %struct.float2* %agg.result, i64 0, > i32 0 > store float %16, float* %agg.result.0, align 8 > %agg.result.1 = getelementptr inb...