Displaying 20 results from an estimated 25 matches for "v1i64".
2018 Jan 12
1
AArch64 v1i64 and v1f64 data types
Hi Tim and all,
A recent commit to the type legalizer has highlighted AArch64's use of v1 data types, could you shine some light on why they've been declared as legal? And any particularly awkward barriers that prevent them from being removed as legal?
cheers,
Sam Parker
Compilation Tools Engineer | Arm
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Arm.com
--------------
2014 Dec 11
2
[LLVMdev] AArch64 codegen question
Hi AArch64 experts -
I'm working on a DAGCombiner patch, and it causes a change in an existing
regression test.
We're generating this:
ext v0.16b, v1.16b, v1.16b, #8
Rather than this:
mov d0, v1.d[1]
Are those logically equivalent? Is one form preferred over the other?
This is the IR test case in /test/CodeGen/AArch64/neon-scalar-copy.ll:
define <1 x i64>
2010 Dec 29
2
[LLVMdev] stack alignment restriction
Hi
Is there a way to enforce a different alignment on vales on stack
as compared to other basic types. Particularly, i would like
characters to be stored at 2 byte boundary.
thanks
dz
2010 Dec 29
0
[LLVMdev] stack alignment restriction
...t;
Check out examples in the lib/Target/* directories. For instance in X86CallingConv.td, we have things like this:
def CC_X86_64_C : CallingConv<[
...
// __m64 vectors get 8-byte stack slots that are 8-byte aligned.
CCIfType<[x86mmx,v1i64], CCAssignToStack<8, 8>>
}
The second parameter to CCAssigneToStack is the alignment for that type.
-bw
2010 Dec 29
1
[LLVMdev] stack alignment restriction
...d at 2 byte boundary.
>>
> Check out examples in the lib/Target/* directories. For instance in X86CallingConv.td, we have things like this:
>
> def CC_X86_64_C : CallingConv<[
> ...
> // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
> CCIfType<[x86mmx,v1i64], CCAssignToStack<8, 8>>
> }
>
> The second parameter to CCAssigneToStack is the alignment for that type.
>
> -bw
>
>
2012 Jul 30
1
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...te it should do bitcast, op, then bitcast, not extend, op and truncate.
"SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
// Vector "promotion" is basically just bitcasting and doing the operation
// in a different type. For example, x86 promotes ISD::AND on v2i32 to
// v1i64."
So following the same logic <4 x i8> bitcasts into a <1 x i32> and then does the ISD::AND and then bitcasts back to <1 x i32>.
Micah
> -----Original Message-----
> From: dag at cray.com [mailto:dag at cray.com]
> Sent: Monday, July 30, 2012 1:15 PM
> To: Vil...
2012 Jul 30
4
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...0, 2012 10:51 AM
> To: Villmow, Micah; Developers Mailing List
> Subject: RE: Vector promotion broken for <2 x [i8|i16]>
>
>
> >Though I am having trouble in understanding how x86 supports the <1 x
> i64> type. Based on looking at the code, it should fail because v1i64
> is not supported on the x86 platform as >far as I can tell.
>
> The Type-Legalizer can handle vector types in the following ways:
> 1. Split - this splits vectors into two halves. For example on SSE4,
> <4 x i64> is split to <2 x i64>
> 2. Widen - this methods...
2016 May 13
2
A question about AArch64 Cortex-A57 subtarget definition
...A57UnitV]> { let Latency = 9; }
def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; }
def A57ReadFPVMA5 : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ]>;
def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>;
```
In this code, an 128bit ASIMD FP multiply accumulate(FMLA/FMLS Q-form) requires
two `A57UnitV`s, meaning that two clock cycles are needed.
^^^^^^^^^^^^^^^^^^^^^^^^^...
2012 Jul 30
2
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...ding the new types so that I can bitcast v2i8 into a v1i16 and then perform the 'and' operation and have legalize types turn the v1i16 into a scalar.
Though I am having trouble in understanding how x86 supports the <1 x i64> type. Based on looking at the code, it should fail because v1i64 is not supported on the x86 platform as far as I can tell.
Micah
From: Rotem, Nadav [mailto:nadav.rotem at intel.com]
Sent: Saturday, July 28, 2012 12:56 PM
To: Villmow, Micah; Developers Mailing List
Subject: RE: Vector promotion broken for <2 x [i8|i16]>
I think that you attached the wro...
2012 Jul 30
2
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...org/svn/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
// Vector "promotion" is basically just bitcasting and doing the operation
// in a different type. For example, x86 promotes ISD::AND on v2i32 to
// v1i64.
EVT VT = Op.getValueType();
assert(Op.getNode()->getNumValues() == 1 &&
"Can't promote a vector with multiple results!");
EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
DebugLoc dl = Op.getDebugLoc();
SmallVector<SDValue, 4> Operands(Op.getN...
2012 Jul 30
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...org/svn/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
// Vector "promotion" is basically just bitcasting and doing the operation
// in a different type. For example, x86 promotes ISD::AND on v2i32 to
// v1i64.
EVT VT = Op.getValueType();
assert(Op.getNode()->getNumValues() == 1 &&
"Can't promote a vector with multiple results!");
EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
DebugLoc dl = Op.getDebugLoc();
SmallVector<SDValue, 4> Operands(Op.getN...
2012 Jul 30
2
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...k/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
> SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
> // Vector "promotion" is basically just bitcasting and doing the
> operation
> // in a different type. For example, x86 promotes ISD::AND on v2i32
> to
> // v1i64.
> EVT VT = Op.getValueType();
> assert(Op.getNode()->getNumValues() == 1 &&
> "Can't promote a vector with multiple results!");
> EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
> DebugLoc dl = Op.getDebugLoc();
> SmallVector<S...
2012 Jul 30
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...:51 AM
> To: Villmow, Micah; Developers Mailing List
> Subject: RE: Vector promotion broken for <2 x [i8|i16]>
>
>
> >Though I am having trouble in understanding how x86 supports the <1
> >x
> i64> type. Based on looking at the code, it should fail because v1i64
> is not supported on the x86 platform as >far as I can tell.
>
> The Type-Legalizer can handle vector types in the following ways:
> 1. Split - this splits vectors into two halves. For example on SSE4,
> <4 x i64> is split to <2 x i64>
> 2. Widen - this methods...
2007 Jun 19
3
[LLVMdev] TargetRegisterClass for Physical Register
...ent says GR32_ is only for 32 bit mode, so it's not
_really_ the case that it's in multiple classes). Does ValueType have
something to do with that?
In the same file, the VR64 register class has the following definition:
def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64], 64,
[MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
So there are multiple ValueTypes here (the scalar registers each only have
one corresponding to the bit size of the register). But still, if I have
physical register MM2, that completely determines its register class....
2012 Jul 30
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
>Though I am having trouble in understanding how x86 supports the <1 x i64> type. Based on looking at the code, it should fail because v1i64 is not supported on the x86 platform as >far as I can tell.
The Type-Legalizer can handle vector types in the following ways:
1. Split - this splits vectors into two halves. For example on SSE4, <4 x i64> is split to <2 x i64>
2. Widen - this methods adds additional vector element...
2012 Jul 30
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
> SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
> // Vector "promotion" is basically just bitcasting and doing the
> operation
> // in a different type. For example, x86 promotes ISD::AND on v2i32
> to
> // v1i64.
> EVT VT = Op.getValueType();
> assert(Op.getNode()->getNumValues() == 1 &&
> "Can't promote a vector with multiple results!");
> EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
> DebugLoc dl = Op.getDebugLoc();
> SmallVector<S...
2012 Jul 30
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
"Villmow, Micah" <Micah.Villmow at amd.com> writes:
> Sorry, <4 x i8> should convert to a <1 x i32>.
Why? I'm really confused.
Shouldn't this converts to a <4 x i32>?
-Dave
2007 Jun 18
2
[LLVMdev] TargetRegisterClass for Physical Register
How do I get the TargetRegisterClass for a physical register?
SSARegMap::getRegClass only works for virtual registers.
-Dave
2007 Jun 19
0
[LLVMdev] TargetRegisterClass for Physical Register
Take a look at getPhysicalRegisterRegClass(
const MRegisterInfo *MRI,
MVT::ValueType VT,
unsigned reg)
in ScheduleDAG.cpp.
--
Christopher Lamb
On Jun 18, 2007, at 4:52 PM, David A. Greene wrote:
> How do I get the TargetRegisterClass for a physical register?
> SSARegMap::getRegClass only works for virtual registers.
>
>
2017 Sep 10
2
Question about quad-register
Hi All,
If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit
register), is it possible mapping quad-register
to v4i32 so that the following example work?
typedef int v4si __attribute__ ((vector_size (16)));
void foo(v4si i) {
v4si j = i;
}
I don't know how to write CallingConv.td to represent the concept of
occupying quad-register R0:R1:R2:R3
once seeing