search for: gettypetopromoteto

v4i8 itself is a legal type, just not on the 'AND' operation. So there seems to be multiple problems here. 1) PromoteVectorOp doesn't handle the case where the types are not the same size, this occurs because #2 2) getTypeToPromoteTo doesn't actual check to see if the type it should promote to makes any sense. 3) PromoteVectorOp also doesn't handle the case where getTypeToPromoteTo returns an invalid type. Micah > -----Original Message----- > From: Rotem, Nadav [mailto:nadav.rotem at intel.com] > Sent: Monday...

If v4i8 is a legal type then getTypeToPromoteTo should return the pair v4i8 and 'legal'. This looks like the root of the problem. -----Original Message----- From: Villmow, Micah [mailto:Micah.Villmow at amd.com] Sent: Monday, July 30, 2012 22:10 To: Rotem, Nadav; Developers Mailing List Subject: RE: Vector promotion broken for <2 x...

...st bitcasting and doing the operation // in a different type. For example, x86 promotes ISD::AND on v2i32 to // v1i64. EVT VT = Op.getValueType(); assert(Op.getNode()->getNumValues() == 1 && "Can't promote a vector with multiple results!"); EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); DebugLoc dl = Op.getDebugLoc(); SmallVector<SDValue, 4> Operands(Op.getNumOperands()); for (unsigned j = 0; j != Op.getNumOperands(); ++j) { if (Op.getOperand(j).getValueType().isVector()) Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j))...

...st bitcasting and doing the operation // in a different type. For example, x86 promotes ISD::AND on v2i32 to // v1i64. EVT VT = Op.getValueType(); assert(Op.getNode()->getNumValues() == 1 && "Can't promote a vector with multiple results!"); EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); DebugLoc dl = Op.getDebugLoc(); SmallVector<SDValue, 4> Operands(Op.getNumOperands()); for (unsigned j = 0; j != Op.getNumOperands(); ++j) { if (Op.getOperand(j).getValueType().isVector()) Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j))...

Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp. The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues. This can be reproduced by setting in any target: setOperationAction(ISD::AND, MVT::i8, Promote);...

.... Promote - this method widens each element in the vector. For example > SSE masks are promoted from <4 x i1> to <4 x i32> > 4. Scalarize - this method coverts vectors with a single element into a > scalar. For example, <1 x i64> into i64. > > >> The function getTypeToPromoteTo will return a <2 x i32> for a <2 x > i8>, <2 x i16> or <4 x i8>. > > The first two conversions look correct, and I assume that your target > declares v2i32 as a legal type. I am not sure how <4 x i8> got there. > Maybe it was first split, and after that...

...Behalf Of Villmow, Micah Sent: Saturday, July 28, 2012 01:54 To: Developers Mailing List Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]> Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp. The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues. This can be reproduced by setting in any target: setOperationAction(ISD::AND, MVT::i8, Promote);...

...romote - this method widens each element in the vector. For example > SSE masks are promoted from <4 x i1> to <4 x i32> 4. Scalarize - this > method coverts vectors with a single element into a scalar. For > example, <1 x i64> into i64. > > >> The function getTypeToPromoteTo will return a <2 x i32> for a <2 x > i8>, <2 x i16> or <4 x i8>. > > The first two conversions look correct, and I assume that your target > declares v2i32 as a legal type. I am not sure how <4 x i8> got there. > Maybe it was first split, and after tha...

...d to <4 x float> 3. Promote - this method widens each element in the vector. For example SSE masks are promoted from <4 x i1> to <4 x i32> 4. Scalarize - this method coverts vectors with a single element into a scalar. For example, <1 x i64> into i64. >> The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The first two conversions look correct, and I assume that your target declares v2i32 as a legal type. I am not sure how <4 x i8> got there. Maybe it was first split, and after that promoted ? From: Rote...

...Hal > > On Fri, 27 Jul 2012 22:54:24 +0000 > "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > > > Vector promotion which is new in LLVM 3.1 is broken for sub32 bit > > types. The problem is in the VectorLegalizer::PromoteVectorOp. The > > function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, > > <2 x i16> or <4 x i8>. The problem is that there are no vectors of > > size 1 defined for i32 or i16. The attached patch fixes these issues. > > > > This can be reproduced by setting in any target: > >...

...lib/CodeGen/SelectionDAG/TargetLowering.cpp | 18 +++++++++--------- 3 files changed, 18 insertions(+), 15 deletions(-) commit 8c6d6ee1bb0c0898dec2c6c5cdeb4c200fb80d1c Author: Patrik Hägglund <patrik.h.hagglund at ericsson.com> Date: Tue Dec 4 16:42:53 2012 +0100 Change TargetLowering::getTypeToPromoteTo to take and return MVTs, instead of EVTs. include/llvm/Target/TargetLowering.h | 8 ++++---- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 12 ++++++------ lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 4 ++-- 3 files changed, 12 insertions(+), 12 deletions(-) commit d3e652d037...

...Jul 2012 22:54:24 +0000 > > "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > > > > > Vector promotion which is new in LLVM 3.1 is broken for sub32 bit > > > types. The problem is in the VectorLegalizer::PromoteVectorOp. The > > > function getTypeToPromoteTo will return a <2 x i32> for a <2 x > > > i8>, <2 x i16> or <4 x i8>. The problem is that there are no > > > i8>vectors of > > > size 1 defined for i32 or i16. The attached patch fixes these > > > issues. > > > > > > Th...

...tring() and EVT::getTypeForEVT. -Hal On Fri, 27 Jul 2012 22:54:24 +0000 "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > Vector promotion which is new in LLVM 3.1 is broken for sub32 bit > types. The problem is in the VectorLegalizer::PromoteVectorOp. The > function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, > <2 x i16> or <4 x i8>. The problem is that there are no vectors of > size 1 defined for i32 or i16. The attached patch fixes these issues. > > This can be reproduced by setting in any target: > setOperationAction(ISD:...

...member) functions, taking an EVT parameter, that asserts if the argument is not an MVT: getRegClassFor, getRepRegClassFor, getRepRegClassCostFor, setTypeAction, getLoadExtAction, isLoadExtLegal, getTruncStoreAction, isTruncStoreLegal, getIndexedLoadAction, getIndexedStoreAction, getCondCodeAction, getTypeToPromoteTo, addRegisterClass Regards, Patrik Hägglund -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20121203/d72ae610/attachment.html>

...Behalf Of Villmow, Micah Sent: Saturday, July 28, 2012 01:54 To: Developers Mailing List Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]> Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp. The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues. This can be reproduced by setting in any target: setOperationAction(ISD::AND, MVT::i8, Promote);...

...and the operations that are legal on that type depend on the current register class. The reason this is a problem is that legalization happens before register-class assignment. Currently, isTypeLegal does not take an opcode parameter, but maybe changing it to depend on the type of operation (like getTypeToPromoteTo does) and the opcode of the node's inputs would help? -Hal On Thu, 24 May 2012 16:11:30 -0500 Sebastian Pop <spop at codeaurora.org> wrote: > Hi, > > On Tue, May 22, 2012 at 11:35 PM, Sebastian Pop <spop at codeaurora.org> > wrote: > > Hi Ivan, > > >...

...e depend on the current register class. The reason > this is a problem is that legalization happens before register-class > assignment. Yes, that's correct. > Currently, isTypeLegal does not take an opcode parameter, but maybe > changing it to depend on the type of operation (like getTypeToPromoteTo > does) and the opcode of the node's inputs would help? I will try to see if I can fix isTypeLegal. Thanks for your helpful comments. Sebastian -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

...ctions, taking an EVT parameter, that asserts if the argument is not an MVT: > > getRegClassFor, getRepRegClassFor, getRepRegClassCostFor, setTypeAction, getLoadExtAction, isLoadExtLegal, getTruncStoreAction, isTruncStoreLegal, getIndexedLoadAction, getIndexedStoreAction, getCondCodeAction, getTypeToPromoteTo, addRegisterClass > Please do. MVT is cheaper than EVT and conceptually cleaner when dealing with physical machine types. EVT should only be used in parts of the code generator that are "pre-legalization" because they can represent arbitrary IR types. Anything that takes a legal...

...ter class. The reason >> this is a problem is that legalization happens before register-class >> assignment. > > Yes, that's correct. > >> Currently, isTypeLegal does not take an opcode parameter, but maybe >> changing it to depend on the type of operation (like getTypeToPromoteTo >> does) and the opcode of the node's inputs would help? > > I will try to see if I can fix isTypeLegal. > Thanks for your helpful comments. Just an idea, you may know that it's possible to custom expand operations with illegal types and it might be useful in this case (co...

Hi, On Tue, May 22, 2012 at 11:35 PM, Sebastian Pop <spop at codeaurora.org> wrote: > Hi Ivan, > > On Tue, May 22, 2012 at 5:09 PM, Ivan Llopard <ivanllopard at gmail.com> wrote: >> Hi Sebastian, >> >> On 22/05/2012 23:25, Sebastian Pop wrote: >>> So my question is how do we specify that for most of the operations i8 >>> should be promoted