search for: setoperationaction

...LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > I'd like to ask you another question (if you don't mind). My EsenciaISelLowering.cpp contains the following code in the EsenciaTargetLowering class constructor: setOperationAction(ISD::BR_CC, MVT::i32, Custom); setOperationAction(ISD::BR_CC, MVT::f32, Custom); setOperationAction(ISD::BR_JT, MVT::Other, Expand); setOperationAction(ISD::BRCOND, MVT::Other, Expand); setOperationAction(ISD::SETCC, MVT::i32, Expan...

...4 ABI) systems currently has a problem handling integer types smaller than 64 bits. This is because the ABI specifies that these types are zero-extended to 64 bits on the stack and the default logic provided in LegalizeDAG does not use that convention. Specifically, for these targets we have: setOperationAction(ISD::VAARG, MVT::Other, Expand); I thought that I could solve this problem by: setOperationAction(ISD::VAARG, MVT::i1, Promote); AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); setOperationAction(ISD::VAARG, MVT::i8, Promote); AddPromotedToType (ISD::VAARG, MVT::i8, MVT::...

...blem handling integer types smaller than 64 bits. > > This is because the ABI specifies that these types are > > zero-extended to 64 bits on the stack and the default logic > > provided in LegalizeDAG does not use that convention. Specifically, > > for these targets we have: setOperationAction(ISD::VAARG, > > MVT::Other, Expand); I thought that I could solve this problem by: > > setOperationAction(ISD::VAARG, MVT::i1, Promote); > > AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); > > setOperationAction(ISD::VAARG, MVT::i8, Promote); > &gt...

...ations, I want to do promote. and to support 64 bit operations, I want to expand. If I can set up the operation actions for the same type globally, then I can avoid to list all the operations with the same action . like // expand type MVT::i64 to MVT::i32 for all the operations instead of “ setOperationAction( ISD::ADD, MVT::i64, Expand); setOperationAction( ISD::SUB, MVT::i64, Expand); setOperationAction( ISD::MUL, MVT::i64, Expand); ….. “ Or LLVM is smart enough to do it buy default? best kevin

I am trying to lower all llvm operations to 8-bit. So far I was trying to have llvm do all that for me using things like: setOperationAction(ISD::ADD, MVT::ii,Promote); setOperationAction(ISD::ADD, MVT::i8,Legal); setOperationAction(ISD::ADD, MVT::i16,Expand); setOperationAction(ISD::ADD, MVT::i32,Expand); However, I keep getting an assertion failure that operation can not be expanded. Now I am thinking maybe LLVM does not lower...

...PromoteVectorOp. The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues. This can be reproduced by setting in any target: setOperationAction(ISD::AND, MVT::i8, Promote); setOperationAction(ISD::AND, MVT::v2i8, Promote); setOperationAction(ISD::AND, MVT::i16, Promote); Let me know if this is good, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachmen...

...tly has a problem handling integer types smaller than 64 bits. > This is because the ABI specifies that these types are zero-extended to > 64 bits on the stack and the default logic provided in LegalizeDAG does > not use that convention. Specifically, for these targets we have: > setOperationAction(ISD::VAARG, MVT::Other, Expand); > I thought that I could solve this problem by: > setOperationAction(ISD::VAARG, MVT::i1, Promote); > AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); > setOperationAction(ISD::VAARG, MVT::i8, Promote); > AddPromotedToTyp...

...g integer types smaller than 64 bits. >>> This is because the ABI specifies that these types are >>> zero-extended to 64 bits on the stack and the default logic >>> provided in LegalizeDAG does not use that convention. Specifically, >>> for these targets we have: setOperationAction(ISD::VAARG, >>> MVT::Other, Expand); I thought that I could solve this problem by: >>> setOperationAction(ISD::VAARG, MVT::i1, Promote); >>> AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); >>> setOperationAction(ISD::VAARG, MVT::i8, Pro...

...will return a <2 x i32> for a <2 x i8>, > > <2 x i16> or <4 x i8>. The problem is that there are no vectors of > > size 1 defined for i32 or i16. The attached patch fixes these issues. > > > > This can be reproduced by setting in any target: > > setOperationAction(ISD::AND, MVT::i8, Promote); > > setOperationAction(ISD::AND, MVT::v2i8, Promote); > > setOperationAction(ISD::AND, MVT::i16, Promote); > > > > Let me know if this is good, > > Micah > > > > > > -- > Hal Finkel > Postdoctoral Appointee > L...

On Wed, 26 Sep 2007 Alireza.Moshtaghi at microchip.com wrote: > I am trying to lower all llvm operations to 8-bit. So far I was trying > to have llvm do all that for me using things like: ok > setOperationAction(ISD::ADD, MVT::ii,Promote); > setOperationAction(ISD::ADD, MVT::i8,Legal); > setOperationAction(ISD::ADD, MVT::i16,Expand); > setOperationAction(ISD::ADD, MVT::i32,Expand); This should work. > However, I keep getting an assertion failure that operation can not be > expanded. On wh...

Hi Renato, > * Have some call-back mechanism, possibly upon a flag > (HasSpecialDivRemLowering), and update the remainder result If you setOperationAction on SDIVREM and UDIVREM to Custom you can expand the rtlib call appropriately yourself. There's precedent for sincos on Darwin systems (both ARM and x86) and in AArch64 for basically every operation on fp128. Cheers. Tim.

...erm "legal" is associated with the Legalize phase. Please see: http://llvm.org/docs/CodeGenerator.html#selectiondag-legalize-phase The x86 backend has a good example of this in llvm/lib/Target/X86/X86ISelLowering.cpp: > if (Subtarget->hasFMA()) { > // Support FMAs! > setOperationAction(ISD::FMA, MVT::f64, Legal); > setOperationAction(ISD::FMA, MVT::f32, Legal); > } > else { > // We don't support FMA. > setOperationAction(ISD::FMA, MVT::f64, Expand); > setOperationAction(ISD::FMA, MVT::f32, Expand); > } Hope that helps, Cameron -----------...

...>, <2 x i16> or <4 x i8>. The problem is that there are no > > > i8>vectors of > > > size 1 defined for i32 or i16. The attached patch fixes these > > > issues. > > > > > > This can be reproduced by setting in any target: > > > setOperationAction(ISD::AND, MVT::i8, Promote); > > > setOperationAction(ISD::AND, MVT::v2i8, Promote); > > > setOperationAction(ISD::AND, MVT::i16, Promote); > > > > > > Let me know if this is good, > > > Micah > > > > > > > > > > > --...

Hi Dmitry, > So instead of setOperationAction(ISD::STORE, MVT::i1, Expand); one > should probably do setOperationAction(ISD::STORE, MVT::i1, Custom); > and implement it in NVPTXTargetLowering::LowerOperation. > > But this issue makes a good point about the code efficiency: I suspect > such expansion will be very ugly in terms of...

Hi Andrea    Thank you your replying.    I do like your letter. Add following to line to MipsISelLowering.cpp. As your words,   @llvm.convert.to.fp16  can compile successfully. However, the runtime is not right. +  setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);+  setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); Robin yalong at multicorewareinc.com  From: Andrea Di BiagioDate: 2014-07-09 14:20To: Matt ArsenaultCC: yalong at multicorewareinc.com; Kevin Qin; llvmdevSubject: Re: [LLVMdev] Help!!!!Help!!!! "...

...AG. >>> You need to express how to legalize/select the BUILD_VECTOR in >>> SelectionDAG to instructions that your target supports. You can look at >>> what other targets are doing. >>> >>> -- >>> Mehdi >>> >>> So I've added setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand); to my code but that generated a following error: fatal error: error in backend: Cannot select: 0x6a84dc8: i32 = extract_vector_elt 0x6a85388, 0x6a813b0 [ORD=9] [ID=16] 0x6a85388: v4i32 = add 0x6a81098, 0x6a81e00 [ORD=8] [ID=15] 0x6a81098: v4i32 =...

Folks, I'm working on bug 16387: "clang doesn't produce ARM EABI-compliant modulo runtime function" http://llvm.org/bugs/show_bug.cgi?id=16387 And I need some pointers. I've changed ARMISelLowering::ARMTargetLowering::ARMTargetLowering() to associate __aeabi_idivmod variants to RTLIB::{U,S}DIVREM_* library calls, but now I need to teach the expansion that on AEABI case,

...> previously submitted test case. For record, it code be done with the > following command: > > $ bugpoint -llc-safe test.ll > > The resulting IR is attached, and it is crashing in the same way. Is > it a valid code? Looks like a bug in the NVPTXISelLowering.cpp: it has "setOperationAction(ISD::STORE, MVT::i1, Expand);", but the legalizer doesn't know how to handle that. -Eli

Hi everyone, Use setOperationAction to tell system the spectied operation does not work with the specified TYPE. Whoes TYPE is it, result type or operand type? Regards -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20091208/71890cb8/attachment...

...tion getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, > <2 x i16> or <4 x i8>. The problem is that there are no vectors of > size 1 defined for i32 or i16. The attached patch fixes these issues. > > This can be reproduced by setting in any target: > setOperationAction(ISD::AND, MVT::i8, Promote); > setOperationAction(ISD::AND, MVT::v2i8, Promote); > setOperationAction(ISD::AND, MVT::i16, Promote); > > Let me know if this is good, > Micah > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory