Displaying 20 results from an estimated 27 matches for "vectorlegalizer".
2016 Jun 28
0
Question about VectorLegalizer::ExpandStore() with v4i1
Hi All,
Can someone comment below question whether it is wrong or not please?
2016-06-25 7:52 GMT+01:00 jingu kang <jaykang10 at gmail.com>:
> Hi All,
>
> I have a problem with VectorLegalizer::ExpandStore() with v4i1.
>
> Let's see a example.
>
> * LLVM IR
> store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27
>
> * SelectionDAG before vector legalization
> ch = store<ST1[%16](align=4), trunc to v4i1> t0, t128, t32, undef:i64
>
> * Sel...
2016 Jun 25
2
Question about VectorLegalizer::ExpandStore() with v4i1
Hi All,
I have a problem with VectorLegalizer::ExpandStore() with v4i1.
Let's see a example.
* LLVM IR
store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27
* SelectionDAG before vector legalization
ch = store<ST1[%16](align=4), trunc to v4i1> t0, t128, t32, undef:i64
* SelectionDAG after vector legalization
ch = store...
2016 Jun 29
0
Question about VectorLegalizer::ExpandStore() with v4i1
...------------------------------------
Message: 8
Date: Tue, 28 Jun 2016 10:57:09 -0700 (PDT)
From: Rob Cameron via llvm-dev <llvm-dev at lists.llvm.org>
To: Ahmed Bougacha <ahmed.bougacha at gmail.com>
Cc: llvm-dev <llvm-dev at lists.llvm.org>
Subject: Re: [llvm-dev] Question about VectorLegalizer::ExpandStore()
with v4i1
Message-ID: <1150997581.449524.1467136629022.JavaMail.zimbra at sfu.ca>
Content-Type: text/plain; charset=utf-8
Hi, Ahmed.
A packed representation, one bit per i1, is natural and best for our
work, for sure. In the Parabix project, we produced very fast text
and...
2016 Jun 28
2
Question about VectorLegalizer::ExpandStore() with v4i1
...AM, jingu kang via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> Hi All,
>
> Can someone comment below question whether it is wrong or not please?
>
> 2016-06-25 7:52 GMT+01:00 jingu kang <jaykang10 at gmail.com>:
>> Hi All,
>>
>> I have a problem with VectorLegalizer::ExpandStore() with v4i1.
>>
>> Let's see a example.
>>
>> * LLVM IR
>> store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27
>>
>> * SelectionDAG before vector legalization
>> ch = store<ST1[%16](align=4), trunc to v4i1> t0, t128...
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...// This file implements the SelectionDAG::LegalizeVectors method.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/Target/TargetLowering.h"
+using namespace llvm;
+
+namespace {
+class VectorLegalizer {
+ SelectionDAG& DAG;
+ TargetLowering& TLI;
+ SDValue UnrollVectorOp(SDValue Op);
+ SDValue PromoteVectorOp(SDValue Op);
+
+ public:
+ bool Run();
+ VectorLegalizer(SelectionDAG& dag) :
+ DAG(dag), TLI(dag.getTargetLoweringInfo()) {}
+};
+
+bool VectorLegalizer::Run() {
+...
2009 May 20
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...// This file implements the SelectionDAG::LegalizeVectors method.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/Target/TargetLowering.h"
+using namespace llvm;
+
+namespace {
+class VectorLegalizer {
+ SelectionDAG& DAG;
+ TargetLowering& TLI;
+ SDValue UnrollVectorOp(SDValue Op);
+ SDValue PromoteVectorOp(SDValue Op);
+
+ public:
+ bool Run();
+ VectorLegalizer(SelectionDAG& dag) :
+ DAG(dag), TLI(dag.getTargetLoweringInfo()) {}
+};
+
+bool VectorLegalizer::Run() {
+...
2012 Jul 27
4
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp.
The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues.
This can be reproduced by setting in any target...
2012 Jul 31
3
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...EVT::getEVTString() and EVT::getTypeForEVT.
>
> -Hal
>
> On Fri, 27 Jul 2012 22:54:24 +0000
> "Villmow, Micah" <Micah.Villmow at amd.com> wrote:
>
> > Vector promotion which is new in LLVM 3.1 is broken for sub32 bit
> > types. The problem is in the VectorLegalizer::PromoteVectorOp. The
> > function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>,
> > <2 x i16> or <4 x i8>. The problem is that there are no vectors of
> > size 1 defined for i32 or i16. The attached patch fixes these issues.
> >
> >...
2012 Aug 01
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...VT.
> >
> > -Hal
> >
> > On Fri, 27 Jul 2012 22:54:24 +0000
> > "Villmow, Micah" <Micah.Villmow at amd.com> wrote:
> >
> > > Vector promotion which is new in LLVM 3.1 is broken for sub32 bit
> > > types. The problem is in the VectorLegalizer::PromoteVectorOp. The
> > > function getTypeToPromoteTo will return a <2 x i32> for a <2 x
> > > i8>, <2 x i16> or <4 x i8>. The problem is that there are no
> > > i8>vectors of
> > > size 1 defined for i32 or i16. The attached patch fi...
2012 Jul 30
1
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
The comments in the code state it should do bitcast, op, then bitcast, not extend, op and truncate.
"SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
// Vector "promotion" is basically just bitcasting and doing the operation
// in a different type. For example, x86 promotes ISD::AND on v2i32 to
// v1i64."
So following the same logic <4 x i8> bitcasts into a <1 x i32> and then does...
2012 Jul 31
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...cations in
lib/VMCore/ValueTypes.cpp to EVT::getEVTString() and
EVT::getTypeForEVT.
-Hal
On Fri, 27 Jul 2012 22:54:24 +0000
"Villmow, Micah" <Micah.Villmow at amd.com> wrote:
> Vector promotion which is new in LLVM 3.1 is broken for sub32 bit
> types. The problem is in the VectorLegalizer::PromoteVectorOp. The
> function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>,
> <2 x i16> or <4 x i8>. The problem is that there are no vectors of
> size 1 defined for i32 or i16. The attached patch fixes these issues.
>
> This can be reproduced...
2012 Jul 30
4
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...iuc.edu]
> On Behalf Of Villmow, Micah
> Sent: Saturday, July 28, 2012 01:54
> To: Developers Mailing List
> Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]>
>
> Vector promotion which is new in LLVM 3.1 is broken for sub32 bit
> types. The problem is in the VectorLegalizer::PromoteVectorOp.
> The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>,
> <2 x i16> or <4 x i8>. The problem is that there are no vectors of size
> 1 defined for i32 or i16. The attached patch fixes these issues.
>
> This can be reproduced...
2012 Jul 28
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah
Sent: Saturday, July 28, 2012 01:54
To: Developers Mailing List
Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]>
Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp.
The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues.
This can be reproduced by setting in any target...
2012 Jul 30
2
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah
Sent: Saturday, July 28, 2012 01:54
To: Developers Mailing List
Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]>
Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp.
The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues.
This can be reproduced by setting in any target...
2012 Jul 30
2
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
Hrmm.... PromoteVectorOp doesn't seem to follow this at all.
http://llvm.org/svn/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
// Vector "promotion" is basically just bitcasting and doing the operation
// in a different type. For example, x86 promotes ISD::AND on v2i32 to
// v1i64.
EVT VT = Op.getValueType();
assert(Op.getNode()->getNumValues() == 1 &&...
2012 Jul 30
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...t: Monday, July 30, 2012 21:26
To: Rotem, Nadav; Developers Mailing List
Subject: RE: Vector promotion broken for <2 x [i8|i16]>
Hrmm.... PromoteVectorOp doesn't seem to follow this at all.
http://llvm.org/svn/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
// Vector "promotion" is basically just bitcasting and doing the operation
// in a different type. For example, x86 promotes ISD::AND on v2i32 to
// v1i64.
EVT VT = Op.getValueType();
assert(Op.getNode()->getNumValues() == 1 &&...
2012 Jul 30
2
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...To: Rotem, Nadav; Developers Mailing List
> Subject: RE: Vector promotion broken for <2 x [i8|i16]>
>
> Hrmm.... PromoteVectorOp doesn't seem to follow this at all.
> http://llvm.org/svn/llvm-
> project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
> SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
> // Vector "promotion" is basically just bitcasting and doing the
> operation
> // in a different type. For example, x86 promotes ISD::AND on v2i32
> to
> // v1i64.
> EVT VT = Op.getValueType();
> assert(Op.getNode()->getN...
2012 Jul 30
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...uc.edu]
> On Behalf Of Villmow, Micah
> Sent: Saturday, July 28, 2012 01:54
> To: Developers Mailing List
> Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]>
>
> Vector promotion which is new in LLVM 3.1 is broken for sub32 bit
> types. The problem is in the VectorLegalizer::PromoteVectorOp.
> The function getTypeToPromoteTo will return a <2 x i32> for a <2 x
> i8>,
> <2 x i16> or <4 x i8>. The problem is that there are no vectors of
> size
> 1 defined for i32 or i16. The attached patch fixes these issues.
>
> This can b...
2012 Jul 30
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah
Sent: Saturday, July 28, 2012 01:54
To: Developers Mailing List
Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]>
Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp.
The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues.
This can be reproduced by setting in any target...
2012 Jul 30
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
...To: Rotem, Nadav; Developers Mailing List
> Subject: RE: Vector promotion broken for <2 x [i8|i16]>
>
> Hrmm.... PromoteVectorOp doesn't seem to follow this at all.
> http://llvm.org/svn/llvm-
> project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
> SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
> // Vector "promotion" is basically just bitcasting and doing the
> operation
> // in a different type. For example, x86 promotes ISD::AND on v2i32
> to
> // v1i64.
> EVT VT = Op.getValueType();
> assert(Op.getNode()->ge...