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Hi, I tried to use the LiveValues pass without success. I did exactly as you wrote me but no luck for me. I am getting this error : [rotem at localhost ~]$ opt -load /home/rotem/Desktop/install/Release/lib/BBPass.so -BBPass < /home/rotem/Desktop/tmp/BBtry.bc > /dev/null Error opening '/home/rotem/Desktop/install/Release/lib/BBPass.so': /home/rotem/Desktop/install/Release/lib/BBPass.so: undefined symbol: _ZN4llvm10LiveVal...

...not the same size, this occurs because #2 2) getTypeToPromoteTo doesn't actual check to see if the type it should promote to makes any sense. 3) PromoteVectorOp also doesn't handle the case where getTypeToPromoteTo returns an invalid type. Micah > -----Original Message----- > From: Rotem, Nadav [mailto:nadav.rotem at intel.com] > Sent: Monday, July 30, 2012 12:06 PM > To: Villmow, Micah; Developers Mailing List > Subject: RE: Vector promotion broken for <2 x [i8|i16]> > > > Notice that PromoteVectorOp is called after the type legalization > legalized al...

If v4i8 is a legal type then getTypeToPromoteTo should return the pair v4i8 and 'legal'. This looks like the root of the problem. -----Original Message----- From: Villmow, Micah [mailto:Micah.Villmow at amd.com] Sent: Monday, July 30, 2012 22:10 To: Rotem, Nadav; Developers Mailing List Subject: RE: Vector promotion broken for <2 x [i8|i16]> v4i8 itself is a legal type, just not on the 'AND' operation. So there seems to be multiple problems here. 1) PromoteVectorOp doesn't handle the case where the types are not the same size, th...

...wever, it breaks when I added v1i16(which I need for the v2i8 case). So I set AddPromotedType(ISD::AND, MVT::v4i8, MVT::v1i32) to get around it. So it seems in this case someone has hit this issue before and added the ability to override promotion rules. > -----Original Message----- > From: Rotem, Nadav [mailto:nadav.rotem at intel.com] > Sent: Monday, July 30, 2012 11:17 AM > To: Villmow, Micah; Developers Mailing List > Subject: RE: Vector promotion broken for <2 x [i8|i16]> > > I don't know how your target architecture looks like, but I suspect > that <4 x...

On Jun 2, 2009, at 5:54 AM, Rotem Varon wrote: > > This questions are on the LiveValues pass: > Do i need to set the "LiveValues" pass in the PassManager as a > prerequisite? if so how do i get the results ? Yes; it's a standard analysis pass. See http://llvm.org/docs/WritingAnLLVMPass.html for informat...

...d only see legal types (Legal types are types that fit into your registers). So, if your target has v2i32, I suspect that v4i8 is an illegal because it has a different size. -----Original Message----- From: Villmow, Micah [mailto:Micah.Villmow at amd.com] Sent: Monday, July 30, 2012 21:26 To: Rotem, Nadav; Developers Mailing List Subject: RE: Vector promotion broken for <2 x [i8|i16]> Hrmm.... PromoteVectorOp doesn't seem to follow this at all. http://llvm.org/svn/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp SDValue VectorLegalizer::PromoteVectorOp(SDValue...

Sorry, <4 x i8> should convert to a <1 x i32>. What currently is happening is that it is returning a <2 x i32> because <1 x i32> does not exist. Micah > -----Original Message----- > From: Rotem, Nadav [mailto:nadav.rotem at intel.com] > Sent: Monday, July 30, 2012 10:51 AM > To: Villmow, Micah; Developers Mailing List > Subject: RE: Vector promotion broken for <2 x [i8|i16]> > > > >Though I am having trouble in understanding how  x86 supports the <1 x >...

greened at obbligato.org (David A. Greene) writes: > "Rotem, Nadav" <nadav.rotem at intel.com> writes: > >> Following the discussion in last week’s LLVM developers conference I >> started working on support for vectors-of-pointers. Vectors of >> pointers are needed for supporting scatter/gather operations and are >> th...

...4> Where the index of the GEP is a vector of indices. I am not against having multiple indices. I just want to start with a basic set of features. Thanks, Nadav -----Original Message----- From: David A. Greene [mailto:greened at obbligato.org] Sent: Tuesday, November 29, 2011 01:57 To: Rotem, Nadav Cc: llvm-commits at cs.uiuc.edu; LLVM Developers Mailing List Subject: Re: [llvm-commits] Vectors of Pointers and Vector-GEP "Rotem, Nadav" <nadav.rotem at intel.com> writes: > Hi, > > Following the discussion in last week’s LLVM developers conference I started wor...

Hi Rotem, Thank to you, and especially to Marina! The problem gone. I'm a bit interested, what is the reason it worked in Win7, and not in Win8. I've recently used Process Explorer to discover, that the call was to ntdll.dll, which in Win8 is loaded to the totally different address. Best regards,...

Hi, I need the Instructions live out, so i will be able to run my pass. One option that i already discussed is to compute it myself. Second option, use the LiveValues Pass(include/llvm/Analysis/LiveValues). This questions are on the LiveValues pass: Do i need to set the "LiveValues" pass in the PassManager as a prerequisite? if so how do i get the results ?How do i get/use the results

"Rotem, Nadav" <nadav.rotem at intel.com> writes: > David, > > Thanks for the support! I sent a detailed email with the overall > plan. But just to reiterate, the GEP would look like this: > > %PV = getelementptr <4 x i32*> %base, <4 x i32> <i32 1, i32 2, i32...

...as some of LLVM's core analysis and transformation passes. -Hal ----- Original Message ----- > From: "Javed Absar" <javed.absar at gmail.com> > To: llvmdev at cs.uiuc.edu > Sent: Sunday, October 7, 2012 10:50:07 AM > Subject: [LLVMdev] LLVM Loop Vectorizer (Nadav Rotem) > > > Hi Nadav (and others who are related to this issue) - > > > I saw some discussions on loop vectorizer that you are planning to > write. Do you foresee using Polyhedral Framework (polly project) in > some way in that. > > > Thanks > J. > __________...

On Oct 7, 2012, at 11:53 PM, Tobias Grosser <tobias at grosser.es> wrote: > As the design of the vectorizer is a very hot topic, I was wondering if there will be a BoF session on the LLVM conference? Nadav, you have not proposed one by accident? I proposed a BoF, and (if accepted) we can start discussing the design of the llvm loop vectorizer and the infrastructure that we need for

On 10/08/2012 06:58 AM, Rao, Prashantha wrote: > It would be great to get "accurate" dependence analysis from polyhedral framework. Anyone working on making polly into analysis+Transforms framework? Polly is already divided into analysis and transformation passes. However, the interface is currently specific to the needs of polyhedral optimizers. If there is interest to use e.g.

...e looks incorrect. The fact that a vector is power-of-two does not guarantee anything about its legality. For example <128 x i64> would pass the condition in the code below, and die on most targets. From: Villmow, Micah [mailto:Micah.Villmow at amd.com] Sent: Friday, July 27, 2012 22:33 To: Rotem, Nadav; Developers Mailing List Subject: RE: TLI.getSetCCResultType() and/or MVT broken by design? if (N0.getOpcode() == ISD::SETCC && (LegalOperations || (!LegalOperations && VT.isPow2VectorType()))) But the comment right after it is: // sext(setcc) -> sext_i...

...ferent legal types. A number of us discussed the possibility of allowing different targets to override the decisions for different types. But at the moment this is only a plan. -----Original Message----- From: Villmow, Micah [mailto:Micah.Villmow at amd.com] Sent: Monday, July 30, 2012 21:05 To: Rotem, Nadav; Developers Mailing List Subject: RE: Vector promotion broken for <2 x [i8|i16]> Sorry, <4 x i8> should convert to a <1 x i32>. What currently is happening is that it is returning a <2 x i32> because <1 x i32> does not exist. Micah > -----Original Message-...

...? -Prashantha -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Sahasrabuddhe, Sameer Sent: Monday, October 08, 2012 9:03 AM To: Hal Finkel; Javed Absar Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] LLVM Loop Vectorizer (Nadav Rotem) > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of Hal Finkel > Sent: Monday, October 08, 2012 1:35 AM > > I'd like to add that, mostly through Tobi's efforts, we were able to have isl (the > int...

...// sext(setcc) -> sext_in_reg(vsetcc) for vectors. // Only do this before legalize for now. if (VT.isVector() && !LegalOperations) { So, these optimizations are never safe in the general case if we can't guarantee that TLI.getSetCCResultType() returns a valid type. From: Rotem, Nadav [mailto:nadav.rotem at intel.com] Sent: Friday, July 27, 2012 12:25 PM To: Villmow, Micah; Developers Mailing List Subject: RE: TLI.getSetCCResultType() and/or MVT broken by design? Hi Micah, I think that getSetCCResultType should only be called for legal types. Disabling it on isPow2Vecto...

Gregory Junker wrote: >>> -----Original Message----- >>> From: Rotem, Nadav [mailto:nadav.rotem at intel.com] >>> Sent: Saturday, July 30, 2011 6:51 AM >>> To: Gregory Junker >>> Subject: RE: [LLVMdev] "Cannot select" error in 2.9 >>> >>> Can you reduce the test with bug-point ? Does it work on ToT ? >> &...