search for: v2i8

...since the mask was generated from a sign extend from an i1… ;-) The problem comes about because the i32 mask and i8 or i16 operands are different widths and expandVSELECT is not equipped to deal with that case. Can you write down the input SDNode ? What types are inputs ? 0x107046d10: v2i8 = vselect 0x107046c10, 0x107046b10, 0x107045e10 [ID=-3] 0x107046c10: v2i32 = setcc 0x107045c10, 0x107045e10, 0x107045f10 [ID=-3] 0x107046b10: v2i8 = BUILD_VECTOR 0x107046a10, 0x107046a10 [ID=-3] 0x107046a10: i8 = Constant<-1> [ID=-3] 0x107045e10: v2i8 = BUILD_VECTO...

...biner.cpp… I changed the ISD::SELECT to the VT.isVector() ? ISD::VSELECT : ISD::SELECT... > Thanks. From the commit message I think that we should only run this optimization on scalars. >> Can you write down the input SDNode ? What types are inputs ? > > 0x107046d10: v2i8 = vselect 0x107046c10, 0x107046b10, 0x107045e10 [ID=-3] > > 0x107046c10: v2i32 = setcc 0x107045c10, 0x107045e10, 0x107045f10 [ID=-3] > 0x107046b10: v2i8 = BUILD_VECTOR 0x107046a10, 0x107046a10 [ID=-3] > 0x107046a10: i8 = Constant<-1> [ID=-3] > 0x1070...

...a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues. This can be reproduced by setting in any target: setOperationAction(ISD::AND, MVT::i8, Promote); setOperationAction(ISD::AND, MVT::v2i8, Promote); setOperationAction(ISD::AND, MVT::i16, Promote); Let me know if this is good, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120727/5e20d318/attachment.html> -------------- next part --...

...a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues. This can be reproduced by setting in any target: setOperationAction(ISD::AND, MVT::i8, Promote); setOperationAction(ISD::AND, MVT::v2i8, Promote); setOperationAction(ISD::AND, MVT::i16, Promote); Let me know if this is good, Micah --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipi...

...gt;. The problem is that there are no vectors of > > size 1 defined for i32 or i16. The attached patch fixes these issues. > > > > This can be reproduced by setting in any target: > > setOperationAction(ISD::AND, MVT::i8, Promote); > > setOperationAction(ISD::AND, MVT::v2i8, Promote); > > setOperationAction(ISD::AND, MVT::i16, Promote); > > > > Let me know if this is good, > > Micah > > > > > > -- > Hal Finkel > Postdoctoral Appointee > Leadership Computing Facility > Argonne National Laboratory --------------...

No, that is correct. I am adding the new types so that I can bitcast v2i8 into a v1i16 and then perform the 'and' operation and have legalize types turn the v1i16 into a scalar. Though I am having trouble in understanding how x86 supports the <1 x i64> type. Based on looking at the code, it should fail because v1i64 is not supported on the x86 platform as...

Hi Richard, > > I did… It originates from an icmp ne <2x i8>, zero initializer followed by a sext of the result 2x i1 to 2x i8. When we visit the SIGN_EXTEND, we generate the ISD::SELECT even though the selector and both operands are vectors. > It sounds like a bug in the dag combine optimization. If you send me the line number I will take a look. >> We should probably

...ctors of > > > size 1 defined for i32 or i16. The attached patch fixes these > > > issues. > > > > > > This can be reproduced by setting in any target: > > > setOperationAction(ISD::AND, MVT::i8, Promote); > > > setOperationAction(ISD::AND, MVT::v2i8, Promote); > > > setOperationAction(ISD::AND, MVT::i16, Promote); > > > > > > Let me know if this is good, > > > Micah > > > > > > > > > > > -- > > Hal Finkel > > Postdoctoral Appointee > > Leadership Computin...

Probably, I misunderstood MemoryVT purpose? Should it be a type that equal to original vector type (e.g. v2i5). Or it is a type of memory area for this vector (e.g. v2i8) ? -Stepan. Stepan Dyatkovskiy wrote: > Hi all. The question about 'load' instruction. > When we promote > v2i5 = load<addr> ;<MemoryVT = v2i5> > to > v2i64 = load<addr> ;<MemoryVT = v2i5> > > should we insert vector shuffling that moves seco...

...x i16> or <4 x i8>. The problem is that there are no vectors of > size 1 defined for i32 or i16. The attached patch fixes these issues. > > This can be reproduced by setting in any target: > setOperationAction(ISD::AND, MVT::i8, Promote); > setOperationAction(ISD::AND, MVT::v2i8, Promote); > setOperationAction(ISD::AND, MVT::i16, Promote); > > Let me know if this is good, > Micah > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory

On 10/30/2012 04:52 PM, Tim Northover wrote: > Hi Heikki, > >> just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))] >> >> gives me error that extloav2i8 is not defined. > > I don't have a target to test this on, but looking at > include/llvm/Target/TargetSelectionDAG.td, there is an "sextloadvi8" > PatFrag, at least. I'd suggest a pattern along the lin...

On Mar 8, 2013, at 2:29 PM, Nadav Rotem <nrotem at apple.com<mailto:nrotem at apple.com>> wrote: Hi Richard, visitSIGN_EXTEND() in DAGCombiner.cpp generates an ISD::SELECT even if VT is a vector, which causes ExpandSELECT() to assert during legalization. I think what's required is to have visitSIGN_EXTEND generate a VSELECT if VT is a vector… ISD::SELECT should be used for

Hi all. The question about 'load' instruction. When we promote v2i5 = load <addr> ; <MemoryVT = v2i5> to v2i64 = load <addr> ;<MemoryVT = v2i5> should we insert vector shuffling that moves second v2i5 item to the second v2i64 item? Or it is still depends from target? Thanks. -Stepan.

...roperly with load/store. But I can't determine exactly what MemoryVT means... -Stepan. Stepan Dyatkovskiy wrote: > Probably, I misunderstood MemoryVT purpose? Should it be a type that > equal to original vector type (e.g. v2i5). Or it is a type of memory > area for this vector (e.g. v2i8) ? > > -Stepan. > > Stepan Dyatkovskiy wrote: >> Hi all. The question about 'load' instruction. >> When we promote >> v2i5 = load<addr> ;<MemoryVT = v2i5> >> to >> v2i64 = load<addr> ;<MemoryVT = v2i5> >> >> s...

...i16 v16i16 = 21, // 16 x i16 v2i32 = 22, // 2 x i32 So, for my platform with the 'and' I promote all i8 and i16 types, so the first type that is legal is v2i32. If I add the v1i32 then it works, however, it breaks when I added v1i16(which I need for the v2i8 case). So I set AddPromotedType(ISD::AND, MVT::v4i8, MVT::v1i32) to get around it. So it seems in this case someone has hit this issue before and added the ability to override promotion rules. > -----Original Message----- > From: Rotem, Nadav [mailto:nadav.rotem at intel.com] > Sent: Mon...

...x i16> or <4 x i8>. The problem is that there are no vectors of size > 1 defined for i32 or i16. The attached patch fixes these issues. > > This can be reproduced by setting in any target: > setOperationAction(ISD::AND, MVT::i8, Promote); > setOperationAction(ISD::AND, MVT::v2i8, Promote); > setOperationAction(ISD::AND, MVT::i16, Promote); > > Let me know if this is good, > Micah > > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential mat...

...i16 v16i16 = 21, // 16 x i16 v2i32 = 22, // 2 x i32 So, for my platform with the 'and' I promote all i8 and i16 types, so the first type that is legal is v2i32. If I add the v1i32 then it works, however, it breaks when I added v1i16(which I need for the v2i8 case). So I set AddPromotedType(ISD::AND, MVT::v4i8, MVT::v1i32) to get around it. So it seems in this case someone has hit this issue before and added the ability to override promotion rules. > -----Original Message----- > From: Rotem, Nadav [mailto:nadav.rotem at intel.com] > Sent: Mon...

.../ 16 x i16 > v2i32 = 22, // 2 x i32 > > So, for my platform with the 'and' I promote all i8 and i16 types, so > the first type that is legal is v2i32. > > If I add the v1i32 then it works, however, it breaks when I added > v1i16(which I need for the v2i8 case). > > So I set AddPromotedType(ISD::AND, MVT::v4i8, MVT::v1i32) to get around > it. So it seems in this case someone has hit this issue before and > added the ability to override promotion rules. > > > -----Original Message----- > > From: Rotem, Nadav [mailto:nadav...

...t; or <4 x i8>. The problem is that there are no vectors of > size > 1 defined for i32 or i16. The attached patch fixes these issues. > > This can be reproduced by setting in any target: > setOperationAction(ISD::AND, MVT::i8, Promote); > setOperationAction(ISD::AND, MVT::v2i8, Promote); > setOperationAction(ISD::AND, MVT::i16, Promote); > > Let me know if this is good, > Micah > > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential ma...

...a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues. This can be reproduced by setting in any target: setOperationAction(ISD::AND, MVT::i8, Promote); setOperationAction(ISD::AND, MVT::v2i8, Promote); setOperationAction(ISD::AND, MVT::i16, Promote); Let me know if this is good, Micah --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipi...