Hi Rail, Below 2 revisions might be of your interest which Detect SAD patterns and emit psadbw instructions on X86.: http://reviews.llvm.org/D14840 http://reviews.llvm.org/D14897 Intrinsics related to absdiff revisons : http://reviews.llvm.org/D10867 http://reviews.llvm.org/D11678 Hope this helps. Regards, Suyog On Sat, May 28, 2016 at 4:20 AM, Rail Shafigulin via llvm-dev < llvm-dev at lists.llvm.org> wrote:> Hi Shahid. > > Do you mind providing a concrete example of X86 code where an intrinsic > was added (preferrable with filenames and line numbers)? I'm having > difficulty tracking down the steps you provided. > > Any help is appreciated. > > > On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad < > Asghar-ahmad.Shahid at amd.com> wrote: > >> Hi Rail, >> >> >> >> We had done this for generation of X86 PSAD (sum of absolute difference) >> instruction through >> >> Llvm intrinsic. Doing this requires following >> >> 1. Define an intrinsic, xyz(), for the required instruction and >> corresponding SDNode >> >> 2. Generate the “call xyz() “ IR based the matched pattern >> >> 3. Map “call xyz()” IR to corresponding SDNode in >> SelectionDagBuilder.cpp >> >> 4. Provide default expansion of the xyz() intrinsic >> >> 5. Legalize type and/or operation >> >> 6. Provide Lowering of intrinsic/SDNode to generate your target >> instruction >> >> >> >> You can visit http://llvm.org/docs/ExtendingLLVM.html for details. >> >> >> >> Regards, >> >> Shahid >> >> >> >> >> >> >> >> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of *Rail >> Shafigulin via llvm-dev >> *Sent:* Monday, April 04, 2016 11:00 PM >> *To:* Das, Dibyendu >> *Cc:* llvm-dev at lists.llvm.org >> *Subject:* Re: [llvm-dev] sum elements in the vector >> >> >> >> Thanks for the pointers. I looked at hadd instructions. They seem to do >> very similar to what I need. Unfortunately as I said before my LLVM >> experience is limited. My understanding is that when I create a new type of >> SDNode I need to specify a pattern for it, so that when LLVM is analyzing >> the code and is seeing a given pattern it would create this particular >> node. I'm really struggling to understand how it is done. So here are the >> problems that I'm having. >> >> >> >> 1. How do I identify that pattern that should be used? >> >> 2. How do I specify a given pattern? >> >> >> >> Do you (or someone else) mind helping me out? >> >> >> >> Any help is appreciated. >> >> >> >> On Mon, Apr 4, 2016 at 9:59 AM, Das, Dibyendu <Dibyendu.Das at amd.com> >> wrote: >> >> This is roughly along the lines of x86 hadd* instructions though the >> semantics of hadd* may not exactly match what you are looking for. This is >> probably more in line with x86/ARM SAD-like instructions but I don’t think >> llvm generates SAD without intrinsics. >> >> >> >> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of *Rail >> Shafigulin via llvm-dev >> *Sent:* Monday, April 04, 2016 9:34 AM >> *To:* llvm-dev <llvm-dev at lists.llvm.org> >> *Subject:* [llvm-dev] sum elements in the vector >> >> >> >> My target has an instruction that adds up all elements in the vector and >> stores the result in a register. I'm trying to implement it in my compiler >> but I'm not sure even where to start. >> >> >> >> I did look at other targets, but they don't seem to have anything like it >> ( I could be wrong. My experience with LLVM is limited, so if I missed it, >> I'd appreciate if someone could point it out ). >> >> >> >> My understanding is that if SDNode for such an instruction doesn't exist >> I have to define one. Unfortunately, I don't know how to do it. I don't >> even know where to start looking. Would someone care to point me in the >> right direction? >> >> >> >> Any help is appreciated. >> >> >> >> -- >> >> Rail Shafigulin >> >> Software Engineer >> Esencia Technologies >> >> >> >> >> >> -- >> >> Rail Shafigulin >> >> Software Engineer >> Esencia Technologies >> > > > > -- > Rail Shafigulin > Software Engineer > Esencia Technologies > > On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad < > Asghar-ahmad.Shahid at amd.com> wrote: > >> Hi Rail, >> >> >> >> We had done this for generation of X86 PSAD (sum of absolute difference) >> instruction through >> >> Llvm intrinsic. Doing this requires following >> >> 1. Define an intrinsic, xyz(), for the required instruction and >> corresponding SDNode >> >> 2. Generate the “call xyz() “ IR based the matched pattern >> >> 3. Map “call xyz()” IR to corresponding SDNode in >> SelectionDagBuilder.cpp >> >> 4. Provide default expansion of the xyz() intrinsic >> >> 5. Legalize type and/or operation >> >> 6. Provide Lowering of intrinsic/SDNode to generate your target >> instruction >> >> >> >> You can visit http://llvm.org/docs/ExtendingLLVM.html for details. >> >> >> >> Regards, >> >> Shahid >> >> >> >> >> >> >> >> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of *Rail >> Shafigulin via llvm-dev >> *Sent:* Monday, April 04, 2016 11:00 PM >> *To:* Das, Dibyendu >> *Cc:* llvm-dev at lists.llvm.org >> *Subject:* Re: [llvm-dev] sum elements in the vector >> >> >> >> Thanks for the pointers. I looked at hadd instructions. They seem to do >> very similar to what I need. Unfortunately as I said before my LLVM >> experience is limited. My understanding is that when I create a new type of >> SDNode I need to specify a pattern for it, so that when LLVM is analyzing >> the code and is seeing a given pattern it would create this particular >> node. I'm really struggling to understand how it is done. So here are the >> problems that I'm having. >> >> >> >> 1. How do I identify that pattern that should be used? >> >> 2. How do I specify a given pattern? >> >> >> >> Do you (or someone else) mind helping me out? >> >> >> >> Any help is appreciated. >> >> >> >> On Mon, Apr 4, 2016 at 9:59 AM, Das, Dibyendu <Dibyendu.Das at amd.com> >> wrote: >> >> This is roughly along the lines of x86 hadd* instructions though the >> semantics of hadd* may not exactly match what you are looking for. This is >> probably more in line with x86/ARM SAD-like instructions but I don’t think >> llvm generates SAD without intrinsics. >> >> >> >> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of *Rail >> Shafigulin via llvm-dev >> *Sent:* Monday, April 04, 2016 9:34 AM >> *To:* llvm-dev <llvm-dev at lists.llvm.org> >> *Subject:* [llvm-dev] sum elements in the vector >> >> >> >> My target has an instruction that adds up all elements in the vector and >> stores the result in a register. I'm trying to implement it in my compiler >> but I'm not sure even where to start. >> >> >> >> I did look at other targets, but they don't seem to have anything like it >> ( I could be wrong. My experience with LLVM is limited, so if I missed it, >> I'd appreciate if someone could point it out ). >> >> >> >> My understanding is that if SDNode for such an instruction doesn't exist >> I have to define one. Unfortunately, I don't know how to do it. I don't >> even know where to start looking. Would someone care to point me in the >> right direction? >> >> >> >> Any help is appreciated. >> >> >> >> -- >> >> Rail Shafigulin >> >> Software Engineer >> Esencia Technologies >> >> >> >> >> >> -- >> >> Rail Shafigulin >> >> Software Engineer >> Esencia Technologies >> > > > > -- > Rail Shafigulin > Software Engineer > Esencia Technologies > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160528/15d3dda4/attachment-0001.html>
Hi Rail,
An additional suggestion w.r.t your example code :
int a[] = {1, 2, 3, 4};
int sum = 0;
for (int i = 0; i < 4; i++)
sum+= a[i];
This loop can unroll and look something like :
sum += a[0] + a[1] + a[2] + a[3]
You can identify above pattern as well to mark intrinsic for horizontal
addition, keeping FP math option into consideration.
Regards,
Suyog
On Sat, May 28, 2016 at 9:29 AM, suyog sarda <sardask01 at gmail.com>
wrote:
> Hi Rail,
>
> Below 2 revisions might be of your interest which Detect SAD patterns and
> emit psadbw instructions on X86.:
>
> http://reviews.llvm.org/D14840
> http://reviews.llvm.org/D14897
>
> Intrinsics related to absdiff revisons :
>
> http://reviews.llvm.org/D10867
> http://reviews.llvm.org/D11678
>
> Hope this helps.
>
> Regards,
> Suyog
>
> On Sat, May 28, 2016 at 4:20 AM, Rail Shafigulin via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> Hi Shahid.
>>
>> Do you mind providing a concrete example of X86 code where an intrinsic
>> was added (preferrable with filenames and line numbers)? I'm having
>> difficulty tracking down the steps you provided.
>>
>> Any help is appreciated.
>>
>>
>> On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad <
>> Asghar-ahmad.Shahid at amd.com> wrote:
>>
>>> Hi Rail,
>>>
>>>
>>>
>>> We had done this for generation of X86 PSAD (sum of absolute
difference)
>>> instruction through
>>>
>>> Llvm intrinsic. Doing this requires following
>>>
>>> 1. Define an intrinsic, xyz(), for the required instruction
and
>>> corresponding SDNode
>>>
>>> 2. Generate the “call xyz() “ IR based the matched pattern
>>>
>>> 3. Map “call xyz()” IR to corresponding SDNode in
>>> SelectionDagBuilder.cpp
>>>
>>> 4. Provide default expansion of the xyz() intrinsic
>>>
>>> 5. Legalize type and/or operation
>>>
>>> 6. Provide Lowering of intrinsic/SDNode to generate your
target
>>> instruction
>>>
>>>
>>>
>>> You can visit http://llvm.org/docs/ExtendingLLVM.html for details.
>>>
>>>
>>>
>>> Regards,
>>>
>>> Shahid
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On
Behalf Of
>>> *Rail Shafigulin via llvm-dev
>>> *Sent:* Monday, April 04, 2016 11:00 PM
>>> *To:* Das, Dibyendu
>>> *Cc:* llvm-dev at lists.llvm.org
>>> *Subject:* Re: [llvm-dev] sum elements in the vector
>>>
>>>
>>>
>>> Thanks for the pointers. I looked at hadd instructions. They seem
to do
>>> very similar to what I need. Unfortunately as I said before my LLVM
>>> experience is limited. My understanding is that when I create a new
type of
>>> SDNode I need to specify a pattern for it, so that when LLVM is
analyzing
>>> the code and is seeing a given pattern it would create this
particular
>>> node. I'm really struggling to understand how it is done. So
here are the
>>> problems that I'm having.
>>>
>>>
>>>
>>> 1. How do I identify that pattern that should be used?
>>>
>>> 2. How do I specify a given pattern?
>>>
>>>
>>>
>>> Do you (or someone else) mind helping me out?
>>>
>>>
>>>
>>> Any help is appreciated.
>>>
>>>
>>>
>>> On Mon, Apr 4, 2016 at 9:59 AM, Das, Dibyendu <Dibyendu.Das at
amd.com>
>>> wrote:
>>>
>>> This is roughly along the lines of x86 hadd* instructions though
the
>>> semantics of hadd* may not exactly match what you are looking for.
This is
>>> probably more in line with x86/ARM SAD-like instructions but I
don’t think
>>> llvm generates SAD without intrinsics.
>>>
>>>
>>>
>>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On
Behalf Of
>>> *Rail Shafigulin via llvm-dev
>>> *Sent:* Monday, April 04, 2016 9:34 AM
>>> *To:* llvm-dev <llvm-dev at lists.llvm.org>
>>> *Subject:* [llvm-dev] sum elements in the vector
>>>
>>>
>>>
>>> My target has an instruction that adds up all elements in the
vector and
>>> stores the result in a register. I'm trying to implement it in
my compiler
>>> but I'm not sure even where to start.
>>>
>>>
>>>
>>> I did look at other targets, but they don't seem to have
anything like
>>> it ( I could be wrong. My experience with LLVM is limited, so if I
missed
>>> it, I'd appreciate if someone could point it out ).
>>>
>>>
>>>
>>> My understanding is that if SDNode for such an instruction
doesn't exist
>>> I have to define one. Unfortunately, I don't know how to do it.
I don't
>>> even know where to start looking. Would someone care to point me in
the
>>> right direction?
>>>
>>>
>>>
>>> Any help is appreciated.
>>>
>>>
>>>
>>> --
>>>
>>> Rail Shafigulin
>>>
>>> Software Engineer
>>> Esencia Technologies
>>>
>>>
>>>
>>>
>>>
>>> --
>>>
>>> Rail Shafigulin
>>>
>>> Software Engineer
>>> Esencia Technologies
>>>
>>
>>
>>
>> --
>> Rail Shafigulin
>> Software Engineer
>> Esencia Technologies
>>
>> On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad <
>> Asghar-ahmad.Shahid at amd.com> wrote:
>>
>>> Hi Rail,
>>>
>>>
>>>
>>> We had done this for generation of X86 PSAD (sum of absolute
difference)
>>> instruction through
>>>
>>> Llvm intrinsic. Doing this requires following
>>>
>>> 1. Define an intrinsic, xyz(), for the required instruction
and
>>> corresponding SDNode
>>>
>>> 2. Generate the “call xyz() “ IR based the matched pattern
>>>
>>> 3. Map “call xyz()” IR to corresponding SDNode in
>>> SelectionDagBuilder.cpp
>>>
>>> 4. Provide default expansion of the xyz() intrinsic
>>>
>>> 5. Legalize type and/or operation
>>>
>>> 6. Provide Lowering of intrinsic/SDNode to generate your
target
>>> instruction
>>>
>>>
>>>
>>> You can visit http://llvm.org/docs/ExtendingLLVM.html for details.
>>>
>>>
>>>
>>> Regards,
>>>
>>> Shahid
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On
Behalf Of
>>> *Rail Shafigulin via llvm-dev
>>> *Sent:* Monday, April 04, 2016 11:00 PM
>>> *To:* Das, Dibyendu
>>> *Cc:* llvm-dev at lists.llvm.org
>>> *Subject:* Re: [llvm-dev] sum elements in the vector
>>>
>>>
>>>
>>> Thanks for the pointers. I looked at hadd instructions. They seem
to do
>>> very similar to what I need. Unfortunately as I said before my LLVM
>>> experience is limited. My understanding is that when I create a new
type of
>>> SDNode I need to specify a pattern for it, so that when LLVM is
analyzing
>>> the code and is seeing a given pattern it would create this
particular
>>> node. I'm really struggling to understand how it is done. So
here are the
>>> problems that I'm having.
>>>
>>>
>>>
>>> 1. How do I identify that pattern that should be used?
>>>
>>> 2. How do I specify a given pattern?
>>>
>>>
>>>
>>> Do you (or someone else) mind helping me out?
>>>
>>>
>>>
>>> Any help is appreciated.
>>>
>>>
>>>
>>> On Mon, Apr 4, 2016 at 9:59 AM, Das, Dibyendu <Dibyendu.Das at
amd.com>
>>> wrote:
>>>
>>> This is roughly along the lines of x86 hadd* instructions though
the
>>> semantics of hadd* may not exactly match what you are looking for.
This is
>>> probably more in line with x86/ARM SAD-like instructions but I
don’t think
>>> llvm generates SAD without intrinsics.
>>>
>>>
>>>
>>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On
Behalf Of
>>> *Rail Shafigulin via llvm-dev
>>> *Sent:* Monday, April 04, 2016 9:34 AM
>>> *To:* llvm-dev <llvm-dev at lists.llvm.org>
>>> *Subject:* [llvm-dev] sum elements in the vector
>>>
>>>
>>>
>>> My target has an instruction that adds up all elements in the
vector and
>>> stores the result in a register. I'm trying to implement it in
my compiler
>>> but I'm not sure even where to start.
>>>
>>>
>>>
>>> I did look at other targets, but they don't seem to have
anything like
>>> it ( I could be wrong. My experience with LLVM is limited, so if I
missed
>>> it, I'd appreciate if someone could point it out ).
>>>
>>>
>>>
>>> My understanding is that if SDNode for such an instruction
doesn't exist
>>> I have to define one. Unfortunately, I don't know how to do it.
I don't
>>> even know where to start looking. Would someone care to point me in
the
>>> right direction?
>>>
>>>
>>>
>>> Any help is appreciated.
>>>
>>>
>>>
>>> --
>>>
>>> Rail Shafigulin
>>>
>>> Software Engineer
>>> Esencia Technologies
>>>
>>>
>>>
>>>
>>>
>>> --
>>>
>>> Rail Shafigulin
>>>
>>> Software Engineer
>>> Esencia Technologies
>>>
>>
>>
>>
>> --
>> Rail Shafigulin
>> Software Engineer
>> Esencia Technologies
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>
>>
>
-------------- next part --------------
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Suyog, Thanks for the reply. Do you know if it is possible to add a new intrinsic without actually modifying core code (ISDOpcodes.h is an example of core code)? I'd like to add this intrinsic with as little code change as possible. On Fri, May 27, 2016 at 8:59 PM, suyog sarda <sardask01 at gmail.com> wrote:> Hi Rail, > > Below 2 revisions might be of your interest which Detect SAD patterns and > emit psadbw instructions on X86.: > > http://reviews.llvm.org/D14840 > http://reviews.llvm.org/D14897 > > Intrinsics related to absdiff revisons : > > http://reviews.llvm.org/D10867 > http://reviews.llvm.org/D11678 > > Hope this helps. > > Regards, > Suyog > > On Sat, May 28, 2016 at 4:20 AM, Rail Shafigulin via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> Hi Shahid. >> >> Do you mind providing a concrete example of X86 code where an intrinsic >> was added (preferrable with filenames and line numbers)? I'm having >> difficulty tracking down the steps you provided. >> >> Any help is appreciated. >> >> >> On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad < >> Asghar-ahmad.Shahid at amd.com> wrote: >> >>> Hi Rail, >>> >>> >>> >>> We had done this for generation of X86 PSAD (sum of absolute difference) >>> instruction through >>> >>> Llvm intrinsic. Doing this requires following >>> >>> 1. Define an intrinsic, xyz(), for the required instruction and >>> corresponding SDNode >>> >>> 2. Generate the “call xyz() “ IR based the matched pattern >>> >>> 3. Map “call xyz()” IR to corresponding SDNode in >>> SelectionDagBuilder.cpp >>> >>> 4. Provide default expansion of the xyz() intrinsic >>> >>> 5. Legalize type and/or operation >>> >>> 6. Provide Lowering of intrinsic/SDNode to generate your target >>> instruction >>> >>> >>> >>> You can visit http://llvm.org/docs/ExtendingLLVM.html for details. >>> >>> >>> >>> Regards, >>> >>> Shahid >>> >>> >>> >>> >>> >>> >>> >>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of >>> *Rail Shafigulin via llvm-dev >>> *Sent:* Monday, April 04, 2016 11:00 PM >>> *To:* Das, Dibyendu >>> *Cc:* llvm-dev at lists.llvm.org >>> *Subject:* Re: [llvm-dev] sum elements in the vector >>> >>> >>> >>> Thanks for the pointers. I looked at hadd instructions. They seem to do >>> very similar to what I need. Unfortunately as I said before my LLVM >>> experience is limited. My understanding is that when I create a new type of >>> SDNode I need to specify a pattern for it, so that when LLVM is analyzing >>> the code and is seeing a given pattern it would create this particular >>> node. I'm really struggling to understand how it is done. So here are the >>> problems that I'm having. >>> >>> >>> >>> 1. How do I identify that pattern that should be used? >>> >>> 2. How do I specify a given pattern? >>> >>> >>> >>> Do you (or someone else) mind helping me out? >>> >>> >>> >>> Any help is appreciated. >>> >>> >>> >>> On Mon, Apr 4, 2016 at 9:59 AM, Das, Dibyendu <Dibyendu.Das at amd.com> >>> wrote: >>> >>> This is roughly along the lines of x86 hadd* instructions though the >>> semantics of hadd* may not exactly match what you are looking for. This is >>> probably more in line with x86/ARM SAD-like instructions but I don’t think >>> llvm generates SAD without intrinsics. >>> >>> >>> >>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of >>> *Rail Shafigulin via llvm-dev >>> *Sent:* Monday, April 04, 2016 9:34 AM >>> *To:* llvm-dev <llvm-dev at lists.llvm.org> >>> *Subject:* [llvm-dev] sum elements in the vector >>> >>> >>> >>> My target has an instruction that adds up all elements in the vector and >>> stores the result in a register. I'm trying to implement it in my compiler >>> but I'm not sure even where to start. >>> >>> >>> >>> I did look at other targets, but they don't seem to have anything like >>> it ( I could be wrong. My experience with LLVM is limited, so if I missed >>> it, I'd appreciate if someone could point it out ). >>> >>> >>> >>> My understanding is that if SDNode for such an instruction doesn't exist >>> I have to define one. Unfortunately, I don't know how to do it. I don't >>> even know where to start looking. Would someone care to point me in the >>> right direction? >>> >>> >>> >>> Any help is appreciated. >>> >>> >>> >>> -- >>> >>> Rail Shafigulin >>> >>> Software Engineer >>> Esencia Technologies >>> >>> >>> >>> >>> >>> -- >>> >>> Rail Shafigulin >>> >>> Software Engineer >>> Esencia Technologies >>> >> >> >> >> -- >> Rail Shafigulin >> Software Engineer >> Esencia Technologies >> >> On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad < >> Asghar-ahmad.Shahid at amd.com> wrote: >> >>> Hi Rail, >>> >>> >>> >>> We had done this for generation of X86 PSAD (sum of absolute difference) >>> instruction through >>> >>> Llvm intrinsic. Doing this requires following >>> >>> 1. Define an intrinsic, xyz(), for the required instruction and >>> corresponding SDNode >>> >>> 2. Generate the “call xyz() “ IR based the matched pattern >>> >>> 3. Map “call xyz()” IR to corresponding SDNode in >>> SelectionDagBuilder.cpp >>> >>> 4. Provide default expansion of the xyz() intrinsic >>> >>> 5. Legalize type and/or operation >>> >>> 6. Provide Lowering of intrinsic/SDNode to generate your target >>> instruction >>> >>> >>> >>> You can visit http://llvm.org/docs/ExtendingLLVM.html for details. >>> >>> >>> >>> Regards, >>> >>> Shahid >>> >>> >>> >>> >>> >>> >>> >>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of >>> *Rail Shafigulin via llvm-dev >>> *Sent:* Monday, April 04, 2016 11:00 PM >>> *To:* Das, Dibyendu >>> *Cc:* llvm-dev at lists.llvm.org >>> *Subject:* Re: [llvm-dev] sum elements in the vector >>> >>> >>> >>> Thanks for the pointers. I looked at hadd instructions. They seem to do >>> very similar to what I need. Unfortunately as I said before my LLVM >>> experience is limited. My understanding is that when I create a new type of >>> SDNode I need to specify a pattern for it, so that when LLVM is analyzing >>> the code and is seeing a given pattern it would create this particular >>> node. I'm really struggling to understand how it is done. So here are the >>> problems that I'm having. >>> >>> >>> >>> 1. How do I identify that pattern that should be used? >>> >>> 2. How do I specify a given pattern? >>> >>> >>> >>> Do you (or someone else) mind helping me out? >>> >>> >>> >>> Any help is appreciated. >>> >>> >>> >>> On Mon, Apr 4, 2016 at 9:59 AM, Das, Dibyendu <Dibyendu.Das at amd.com> >>> wrote: >>> >>> This is roughly along the lines of x86 hadd* instructions though the >>> semantics of hadd* may not exactly match what you are looking for. This is >>> probably more in line with x86/ARM SAD-like instructions but I don’t think >>> llvm generates SAD without intrinsics. >>> >>> >>> >>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of >>> *Rail Shafigulin via llvm-dev >>> *Sent:* Monday, April 04, 2016 9:34 AM >>> *To:* llvm-dev <llvm-dev at lists.llvm.org> >>> *Subject:* [llvm-dev] sum elements in the vector >>> >>> >>> >>> My target has an instruction that adds up all elements in the vector and >>> stores the result in a register. I'm trying to implement it in my compiler >>> but I'm not sure even where to start. >>> >>> >>> >>> I did look at other targets, but they don't seem to have anything like >>> it ( I could be wrong. My experience with LLVM is limited, so if I missed >>> it, I'd appreciate if someone could point it out ). >>> >>> >>> >>> My understanding is that if SDNode for such an instruction doesn't exist >>> I have to define one. Unfortunately, I don't know how to do it. I don't >>> even know where to start looking. Would someone care to point me in the >>> right direction? >>> >>> >>> >>> Any help is appreciated. >>> >>> >>> >>> -- >>> >>> Rail Shafigulin >>> >>> Software Engineer >>> Esencia Technologies >>> >>> >>> >>> >>> >>> -- >>> >>> Rail Shafigulin >>> >>> Software Engineer >>> Esencia Technologies >>> >> >> >> >> -- >> Rail Shafigulin >> Software Engineer >> Esencia Technologies >> >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org >> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >> >> >-- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160530/999a5fd7/attachment-0001.html>
Are D10867 and D11678 part of the trunk? I've just checked out latest LLVM and was not able to find a UABSDIFF and SBSDIFF nodes in ISDOpcodes.h On Fri, May 27, 2016 at 8:59 PM, suyog sarda <sardask01 at gmail.com> wrote:> Hi Rail, > > Below 2 revisions might be of your interest which Detect SAD patterns and > emit psadbw instructions on X86.: > > http://reviews.llvm.org/D14840 > http://reviews.llvm.org/D14897 > > Intrinsics related to absdiff revisons : > > http://reviews.llvm.org/D10867 > http://reviews.llvm.org/D11678 > > Hope this helps. > > Regards, > Suyog > > On Sat, May 28, 2016 at 4:20 AM, Rail Shafigulin via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> Hi Shahid. >> >> Do you mind providing a concrete example of X86 code where an intrinsic >> was added (preferrable with filenames and line numbers)? I'm having >> difficulty tracking down the steps you provided. >> >> Any help is appreciated. >> >> >> On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad < >> Asghar-ahmad.Shahid at amd.com> wrote: >> >>> Hi Rail, >>> >>> >>> >>> We had done this for generation of X86 PSAD (sum of absolute difference) >>> instruction through >>> >>> Llvm intrinsic. Doing this requires following >>> >>> 1. Define an intrinsic, xyz(), for the required instruction and >>> corresponding SDNode >>> >>> 2. Generate the “call xyz() “ IR based the matched pattern >>> >>> 3. Map “call xyz()” IR to corresponding SDNode in >>> SelectionDagBuilder.cpp >>> >>> 4. Provide default expansion of the xyz() intrinsic >>> >>> 5. Legalize type and/or operation >>> >>> 6. Provide Lowering of intrinsic/SDNode to generate your target >>> instruction >>> >>> >>> >>> You can visit http://llvm.org/docs/ExtendingLLVM.html for details. >>> >>> >>> >>> Regards, >>> >>> Shahid >>> >>> >>> >>> >>> >>> >>> >>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of >>> *Rail Shafigulin via llvm-dev >>> *Sent:* Monday, April 04, 2016 11:00 PM >>> *To:* Das, Dibyendu >>> *Cc:* llvm-dev at lists.llvm.org >>> *Subject:* Re: [llvm-dev] sum elements in the vector >>> >>> >>> >>> Thanks for the pointers. I looked at hadd instructions. They seem to do >>> very similar to what I need. Unfortunately as I said before my LLVM >>> experience is limited. My understanding is that when I create a new type of >>> SDNode I need to specify a pattern for it, so that when LLVM is analyzing >>> the code and is seeing a given pattern it would create this particular >>> node. I'm really struggling to understand how it is done. So here are the >>> problems that I'm having. >>> >>> >>> >>> 1. How do I identify that pattern that should be used? >>> >>> 2. How do I specify a given pattern? >>> >>> >>> >>> Do you (or someone else) mind helping me out? >>> >>> >>> >>> Any help is appreciated. >>> >>> >>> >>> On Mon, Apr 4, 2016 at 9:59 AM, Das, Dibyendu <Dibyendu.Das at amd.com> >>> wrote: >>> >>> This is roughly along the lines of x86 hadd* instructions though the >>> semantics of hadd* may not exactly match what you are looking for. This is >>> probably more in line with x86/ARM SAD-like instructions but I don’t think >>> llvm generates SAD without intrinsics. >>> >>> >>> >>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of >>> *Rail Shafigulin via llvm-dev >>> *Sent:* Monday, April 04, 2016 9:34 AM >>> *To:* llvm-dev <llvm-dev at lists.llvm.org> >>> *Subject:* [llvm-dev] sum elements in the vector >>> >>> >>> >>> My target has an instruction that adds up all elements in the vector and >>> stores the result in a register. I'm trying to implement it in my compiler >>> but I'm not sure even where to start. >>> >>> >>> >>> I did look at other targets, but they don't seem to have anything like >>> it ( I could be wrong. My experience with LLVM is limited, so if I missed >>> it, I'd appreciate if someone could point it out ). >>> >>> >>> >>> My understanding is that if SDNode for such an instruction doesn't exist >>> I have to define one. Unfortunately, I don't know how to do it. I don't >>> even know where to start looking. Would someone care to point me in the >>> right direction? >>> >>> >>> >>> Any help is appreciated. >>> >>> >>> >>> -- >>> >>> Rail Shafigulin >>> >>> Software Engineer >>> Esencia Technologies >>> >>> >>> >>> >>> >>> -- >>> >>> Rail Shafigulin >>> >>> Software Engineer >>> Esencia Technologies >>> >> >> >> >> -- >> Rail Shafigulin >> Software Engineer >> Esencia Technologies >> >> On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad < >> Asghar-ahmad.Shahid at amd.com> wrote: >> >>> Hi Rail, >>> >>> >>> >>> We had done this for generation of X86 PSAD (sum of absolute difference) >>> instruction through >>> >>> Llvm intrinsic. Doing this requires following >>> >>> 1. Define an intrinsic, xyz(), for the required instruction and >>> corresponding SDNode >>> >>> 2. Generate the “call xyz() “ IR based the matched pattern >>> >>> 3. Map “call xyz()” IR to corresponding SDNode in >>> SelectionDagBuilder.cpp >>> >>> 4. Provide default expansion of the xyz() intrinsic >>> >>> 5. Legalize type and/or operation >>> >>> 6. Provide Lowering of intrinsic/SDNode to generate your target >>> instruction >>> >>> >>> >>> You can visit http://llvm.org/docs/ExtendingLLVM.html for details. >>> >>> >>> >>> Regards, >>> >>> Shahid >>> >>> >>> >>> >>> >>> >>> >>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of >>> *Rail Shafigulin via llvm-dev >>> *Sent:* Monday, April 04, 2016 11:00 PM >>> *To:* Das, Dibyendu >>> *Cc:* llvm-dev at lists.llvm.org >>> *Subject:* Re: [llvm-dev] sum elements in the vector >>> >>> >>> >>> Thanks for the pointers. I looked at hadd instructions. They seem to do >>> very similar to what I need. Unfortunately as I said before my LLVM >>> experience is limited. My understanding is that when I create a new type of >>> SDNode I need to specify a pattern for it, so that when LLVM is analyzing >>> the code and is seeing a given pattern it would create this particular >>> node. I'm really struggling to understand how it is done. So here are the >>> problems that I'm having. >>> >>> >>> >>> 1. How do I identify that pattern that should be used? >>> >>> 2. How do I specify a given pattern? >>> >>> >>> >>> Do you (or someone else) mind helping me out? >>> >>> >>> >>> Any help is appreciated. >>> >>> >>> >>> On Mon, Apr 4, 2016 at 9:59 AM, Das, Dibyendu <Dibyendu.Das at amd.com> >>> wrote: >>> >>> This is roughly along the lines of x86 hadd* instructions though the >>> semantics of hadd* may not exactly match what you are looking for. This is >>> probably more in line with x86/ARM SAD-like instructions but I don’t think >>> llvm generates SAD without intrinsics. >>> >>> >>> >>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of >>> *Rail Shafigulin via llvm-dev >>> *Sent:* Monday, April 04, 2016 9:34 AM >>> *To:* llvm-dev <llvm-dev at lists.llvm.org> >>> *Subject:* [llvm-dev] sum elements in the vector >>> >>> >>> >>> My target has an instruction that adds up all elements in the vector and >>> stores the result in a register. I'm trying to implement it in my compiler >>> but I'm not sure even where to start. >>> >>> >>> >>> I did look at other targets, but they don't seem to have anything like >>> it ( I could be wrong. My experience with LLVM is limited, so if I missed >>> it, I'd appreciate if someone could point it out ). >>> >>> >>> >>> My understanding is that if SDNode for such an instruction doesn't exist >>> I have to define one. Unfortunately, I don't know how to do it. I don't >>> even know where to start looking. Would someone care to point me in the >>> right direction? >>> >>> >>> >>> Any help is appreciated. >>> >>> >>> >>> -- >>> >>> Rail Shafigulin >>> >>> Software Engineer >>> Esencia Technologies >>> >>> >>> >>> >>> >>> -- >>> >>> Rail Shafigulin >>> >>> Software Engineer >>> Esencia Technologies >>> >> >> >> >> -- >> Rail Shafigulin >> Software Engineer >> Esencia Technologies >> >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org >> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >> >> >-- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160530/a04e4829/attachment.html>
Suyog,> > Thanks for the reply. Do you know if it is possible to add a new intrinsic > without actually modifying core code (ISDOpcodes.h is an example of core > code)? I'd like to add this intrinsic with as little code change as > possible. > >There were attempts to identify this pattern (and similar other) at selectionDAG level and emit vector code customized for a backend. See example - https://llvm.org/bugs/show_bug.cgi?id=20035 and thread http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20140616/221763.html As reviewed, this made very specific to a given target and it was suggested to handle these patterns at IR level. At IR level, attempt was made to catch this pattern in Loop/SLP(unrolled straight line code) vectorizer and use TTI cost info to vectorize the pattern. This was again clumsy. As James and Shahid pointed out, intrinsics are the best shot to vectorize this pattern to make it more generic. This generally follows the steps listed by Shahid : 1. Define an intrinsic, xyz(), for the required instruction and corresponding SDNode 2. Generate the “call xyz() “ IR based the matched pattern 3. Map “call xyz()” IR to corresponding SDNode in SelectionDagBuilder.cpp 4. Provide default expansion of the xyz() intrinsic 5. Legalize type and/or operation 6. Provide Lowering of intrinsic/SDNode to generate your target instruction When a pattern is identified and marked with intrinsic at IR level, a corresponding SDNode will be generated when converting IR to SelectionDAG. This SDNode can then be legalize/expanded/lowered to specific target when lowering to target machine code. For this intrinsic specific SDNode, IMO you will have to add the entries in ISDOpcodes.h. I don't see any harm or big change in adding them. As you know, the pattern listed in above discussions is commonly occurring pattern and hence need to be identified at IR level via intrinsics. Every target has its own way to handle these patterns - as far as i know X86 will have single instruction PSAD while AArch64 will handle it in two steps. This variance can be handled at DAGLowering and target code generation phase (and this will be highly acceptable to land in trunk code since it solves the issue in clean and generic way). Not sure if D10867 and D11678 were reverted later, but i think these can serve your purpose as an example to add intrinsic and generate code. Regards, Suyog -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160531/d9ff41a7/attachment.html>