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...point it out ). My understanding is that if SDNode for such an instruction doesn't exist I have to define one. Unfortunately, I don't know how to do it. I don't even know where to start looking. Would someone care to point me in the right direction? Any help is appreciated. -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160404/0d8eed60/attachment.html>

...Detect SAD patterns and emit psadbw instructions on X86.: http://reviews.llvm.org/D14840 http://reviews.llvm.org/D14897 Intrinsics related to absdiff revisons : http://reviews.llvm.org/D10867 http://reviews.llvm.org/D11678 Hope this helps. Regards, Suyog On Sat, May 28, 2016 at 4:20 AM, Rail Shafigulin via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi Shahid. > > Do you mind providing a concrete example of X86 code where an intrinsic > was added (preferrable with filenames and line numbers)? I'm having > difficulty tracking down the steps you provided. > > Any...

...to generate your target > instruction > > > > You can visit http://llvm.org/docs/ExtendingLLVM.html for details. > > > > Regards, > > Shahid > > > > > > > > *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of *Rail > Shafigulin via llvm-dev > *Sent:* Monday, April 04, 2016 11:00 PM > *To:* Das, Dibyendu > *Cc:* llvm-dev at lists.llvm.org > *Subject:* Re: [llvm-dev] sum elements in the vector > > > > Thanks for the pointers. I looked at hadd instructions. They seem to do > very similar to what I...

...A, GPR:$rB))`. It then becomes a simple substitution. > This is a DAG because there all nodes are directed and acyclic. > Am I correct in my understanding that each node can either be a register or of type SDNode defined in TargetSelectionDAG.td? > On Thu, Jan 28, 2016 at 7:33 PM, Rail Shafigulin via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> I'm confused about how to specify DAG patterns for a given instruction >> >> Here is an example for my target >> >> class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode> >>...

...ny instruction to directly represent “sum of elements in a vector” and generate your particular instruction.However, you can do it without intrinsic by pattern matching the LLVM-IRs representing “sum of elements in vector” to your particular instruction in DAGCombiner. Regards, Shahid From: Rail Shafigulin [mailto:rail at esenciatech.com] Sent: Monday, May 09, 2016 11:59 PM To: Shahid, Asghar-ahmad; llvm-dev Cc: Das, Dibyendu Subject: Re: [llvm-dev] sum elements in the vector I'm a little confused. Here is why. I was able to add a vector add instruction to my target without using any intrinsics...

...using normal vector operation, and then the final scalar value can be computed using a single horizontal operation. MartinO From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Chandler Carruth via llvm-dev Sent: 16 May 2016 2:16 To: Shahid, Asghar-ahmad; Rail Shafigulin; llvm-dev; Hal Finkel Subject: Re: [llvm-dev] sum elements in the vector I'm starting to think we should directly implement horizontal operations on vector types. My suspicion is that coming up with a nice model for this would help us a lot with things like: - Idiom recognition of redu...

...iler will be able to target this new instruction (sum elements in a vector) if it is implemented as an intrinsic or the user will have to specifically invoke an instrinsic. Pardon if questions seem dumb, I'm still learning things. Any help is appreciated. On Fri, May 6, 2016 at 1:51 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > Thanks for the reply. These steps will add an instruction as an intrinsic. > Is it possible to add an actual new instruction so that a compiler could > target it during an optimization? How hard is it to do it? Is that a > realistic objective. &...

> On Feb 1, 2016, at 16:53, Rail Shafigulin <rail at esenciatech.com> wrote: > > > > On Fri, Jan 29, 2016 at 10:03 PM, Matt Arsenault <arsenm2 at gmail.com <mailto:arsenm2 at gmail.com>> wrote: > > > On Jan 29, 2016, at 13:25, Rail Shafigulin via llvm-dev <llvm-dev at lists.llvm.org <mailto:ll...

...your particular instruction.However, you can do it without > intrinsic by pattern matching the > > LLVM-IRs representing “sum of elements in vector” to your particular > instruction in DAGCombiner. > > > > Regards, > > Shahid > > > > > > *From:* Rail Shafigulin [mailto:rail at esenciatech.com] > *Sent:* Monday, May 09, 2016 11:59 PM > *To:* Shahid, Asghar-ahmad; llvm-dev > *Cc:* Das, Dibyendu > > > *Subject:* Re: [llvm-dev] sum elements in the vector > > > > I'm a little confused. Here is why. > > > > I was ab...

...We “could” write patterns for each of the permutations, but it is verbose, and in practice most people only write it one way anyway. The 8-lane equivalent has TableGen left thinking for quite a long time, and the 16-lane equivalent seems to hang TableGen. MartinO From: Rail Shafigulin [mailto:rail at esenciatech.com] Sent: 16 May 2016 23:50 To: Martin J. O'Riordan Cc: LLVM Developers Subject: Re: [llvm-dev] sum elements in the vector On Mon, May 16, 2016 at 3:11 AM, Martin J. O'Riordan via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.ll...

On Fri, Jan 29, 2016 at 11:39 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > > On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> > wrote: > >> Try visualising the DAG like this. >> >> ``` >> ---- GPR:$rA >> / >...

...to the block, and then have a COPY instruction that would transfer it into a virtual register, which would then be used in the ADDI. Since you are using llvm 3.5, that may still be the case for you. I'm not sure whether this is still necessary in ToT. -Krzysztof On 4/27/2016 6:08 PM, Rail Shafigulin wrote: > I'm attaching an output of -mllvm -debug command. The output is large > but i'm hoping it contains everything that is needed. If anyone needs > more, just ask. > > Any help in resolving the issue is appreciated. > > On Wed, Apr 27, 2016 at 2:52 PM, Rail Shafigu...

Is there a way to enable/disable target features through clang? I found this, https://github.com/avr-llvm/llvm/issues/9, but this seems to be talking about llc -mattr=+feature1,-feature2... Is there something equivalent for clang? -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160502/da652ea8/attachment.html>

> On Mar 18, 2016, at 1:47 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > > Yes this IR does not build or shuffle any vector. Try to write a function that takes 8 ints and a pointer to a <4xi32>, builds two vectors with the 8 ints, > > This might sound like a dumb question, but how does one build a vector of in...

On Thu, Feb 18, 2016 at 11:22 AM, Jonathan Roelofs < jonathan at codesourcery.com> wrote: > > > On 2/18/16 12:19 PM, Rail Shafigulin via llvm-dev wrote: > >> >> >> On Thu, Feb 18, 2016 at 10:50 AM, Krzysztof Parzyszek via llvm-dev >> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> On 2/18/2016 12:43 PM, Rail Shafigulin via llvm-dev wrote: >&g...

On Tue, Feb 2, 2016 at 1:41 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > Let me clarify. >> >> I'm not sure I understand what you are saying. Let me post more >> information. >> >> Here is what I have defined for Escalasetflag >> >> def Escalasetflag : SDNode<"Esc...

On 4/28/2016 2:11 PM, Rail Shafigulin wrote: > > On Thu, Apr 28, 2016 at 6:13 AM, Krzysztof Parzyszek > <kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote: > > > IIRC, > > What is IIRC? If I remember correctly... -Krzysztof -- Qualcomm Innovation Center, Inc. is a member o...

On Fri, Mar 18, 2016 at 2:03 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > On Fri, Mar 18, 2016 at 1:53 PM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> >> On Mar 18, 2016, at 1:47 PM, Rail Shafigulin <rail at esenciatech.com> >> wrote: >> >> Yes this IR does not build or...

...ny instructions (other than COPY) that use hardware > (allocatable) registers? > How do I find that out? > Could you show the instructions in the scheduling range? > How can I see instructions in the current scheduling range? > -Krzysztof > > > On 4/27/2016 3:44 PM, Rail Shafigulin wrote: > >> Thanks for the suggestion. >> >> I tried your fix. It worked for my particular case, but then I got a >> following error: >> >> clang-3.5: >> >> /home/rail/projects/escala_llvm/trunk/llvm-or1k/lib/CodeGen/RegisterPressure.cpp:39: >&g...

On Thu, Feb 18, 2016 at 10:50 AM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 2/18/2016 12:43 PM, Rail Shafigulin via llvm-dev wrote: > >> >> LLVM ERROR: Cannot select: 0x3284268: glue = EsenciaISD::SET_FLAG >> 0x3283608, 0x3283710, 0x3283e48 [ORD=3] [ID=11] >> 0x3283608: i32,ch = CopyFromReg 0x3257980, 0x3283500 [ORD=1] [ID=9] >> 0x3283500: i32 = Register %vreg5 [ID=1]...