search for: shahid

So IMO, if we modify the VF calculation for targets/subtargets using TTI where higher VF is supported The vectorizer’s scope will become wider. Did/do you foresee any issue with this? Thanks, Shahid From: Nadav Rotem [mailto:nrotem at apple.com] Sent: Saturday, December 13, 2014 2:47 AM To: Shahid, Asghar-ahmad Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Vectorization factor limitation in Loop Vectorizer Hi Shahid, On Dec 10, 2014, at 10:48 PM, Shahid, Asghar-ahmad <Asghar-ahmad.Sh...

I am having problem with Samba 2.x. I am be able to login to Samba without a problem :). When I login to "Shahid" account it directed to "/home/shahid" but I can still can see another user home dir too? why that so like I login as "shahid" account then can see "/home/shahid" but why I can see " /home/test" too - it shouldnt be? Each user should have own homedir...

Hi Shahid, Thank you so much for your response. You suggested approach is what I am right now using. However, it seems that the overhead is a little bit high because we are introducing two more instructions. I was wondering if there was a cheaper way to do it. Best, Zhi On Mon, May 4, 2015 at 2:12 AM, Sha...

...at having both absd/hadd and sad are compatible with the discussions going on in other threads, for example my thread about min and max. Given that those two intrinsics are fairly trivial to match , I don't see the need to have two different canonical forms. James On Mon, 4 May 2015 at 07:55, Shahid, Asghar-ahmad < Asghar-ahmad.Shahid at amd.com> wrote: > Hi Devs, > > Pinging..., as didn't get any response yet. Or shall I assume it is > acceptable to all? > > Regards, > Shahid > > > -----Original Message----- > > From: llvmdev-bounces at cs.uiuc.e...

...ion factor(VF) of 8, However it is not doing so due to the widest type calculation done for the blocks inside the loop. May be I am missing something, however, I am curious to know why Loop Vectorizer limits the profitability check to widest type and not allowing for other narrower type? Regards, Shahid -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20141211/4389cec8/attachment.html>

Thanks, Shahid. It is fixed now. On Fri, Apr 17, 2015 at 8:50 PM, Shahid, Asghar-ahmad < Asghar-ahmad.Shahid at amd.com> wrote: > Hi zhi, > > > > You have to also pass the value type to getDecalaration() API such as > > > > Value* sqrtv = Intrinsic::getDeclaration(M, Intrinsic:...

On 4 May 2015 at 08:37, Shahid, Asghar-ahmad <Asghar-ahmad.Shahid at amd.com> wrote: > My worry is regarding the query for cost calculation for specific SAD > instructions such as ‘psad’ (X86) or ‘usad’ (ARM) in Loop Vectorizer. Hi Shahid, The vectorizer's cost model has the ability to return different costs fo...

...;PSAD" instruction. W/ llvm.absd() and llvm.hadd() VC2 = Cost associated with "absolute diff" + "horizontal add" ( ??? ) As I will be querying with getIntrinsicCost(ID) for these two intrinsics separately, Will VC1==VC2? May be I am missing something obvious? Regards, Shahid > -----Original Message----- > From: Renato Golin [mailto:renato.golin at linaro.org] > Sent: Tuesday, May 05, 2015 7:28 PM > To: Shahid, Asghar-ahmad > Cc: James Molloy; llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics > > On 4...

...e best way forward for now. Sorry that I could not get what exactly you mean with "heuristics". Is it the "intrinsics approach" itself or something else? BTW, now my plan is to just add the two intrinsics for 'absolute difference' and 'horizontal add'. Regards, Shahid > -----Original Message----- > From: Renato Golin [mailto:renato.golin at linaro.org] > Sent: Wednesday, May 06, 2015 3:22 PM > To: Shahid, Asghar-ahmad > Cc: James Molloy; llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics > > On...

Hello, Can someone recommend me where is best place to find Asterisk Expert/Consultant for freelance work? If you are interested to work as a freelancer, you can email me directly. Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.digium.com/pipermail/asterisk-users/attachments/20150902/5a99cbfe/attachment.html>

...LLVM does not have any instruction to directly represent “sum of elements in a vector” and generate your particular instruction.However, you can do it without intrinsic by pattern matching the LLVM-IRs representing “sum of elements in vector” to your particular instruction in DAGCombiner. Regards, Shahid From: Rail Shafigulin [mailto:rail at esenciatech.com] Sent: Monday, May 09, 2016 11:59 PM To: Shahid, Asghar-ahmad; llvm-dev Cc: Das, Dibyendu Subject: Re: [llvm-dev] sum elements in the vector I'm a little confused. Here is why. I was able to add a vector add instruction to my target with...

...intrinsics based on the target's Backend support. Having these intrinsic will also help in cost modeling for these idioms which is complex down the lane. Pls find attached a patch regarding this which is incomplete & dirty at this moment, however, it may help in this discussion. Regards, Shahid -------------- next part -------------- A non-text attachment was scrubbed... Name: absd_hadd_sad_intrinsic.patch Type: application/octet-stream Size: 30121 bytes Desc: absd_hadd_sad_intrinsic.patch URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150501/facd5cdb/attachment.obj>

Hi Renato, That’s right. I agree with your *pattern vs complexity* thinking. So I would drop llvm.sad() and go ahead with the remaining two. Does it make sense in general? Regards, Shahid > -----Original Message----- > From: Renato Golin [mailto:renato.golin at linaro.org] > Sent: Tuesday, May 05, 2015 8:40 PM > To: Shahid, Asghar-ahmad > Cc: James Molloy; llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics > > On 5...

...atterns that use horizontal arithmetic - Ability to use horizontal operations in SLPVectorizer - Significantly easier cost modeling of vectorizing loops with reductions in LoopVectorize - Other things I've not thought of? Curious what others think? -Chandler On Wed, May 11, 2016 at 10:07 PM Shahid, Asghar-ahmad via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > why in order to add this particular instruction (sum elements in a > vector) I need to add an insrinsic? > > Adding intrinsic is not the only way, it is one of the way and user > WILL-NOT be required to inv...

...at a time can be computed using normal vector operation, and then the final scalar value can be computed using a single horizontal operation. MartinO From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Chandler Carruth via llvm-dev Sent: 16 May 2016 2:16 To: Shahid, Asghar-ahmad; Rail Shafigulin; llvm-dev; Hal Finkel Subject: Re: [llvm-dev] sum elements in the vector I'm starting to think we should directly implement horizontal operations on vector types. My suspicion is that coming up with a nice model for this would help us a lot with things lik...

...lvm.org/D14840 http://reviews.llvm.org/D14897 Intrinsics related to absdiff revisons : http://reviews.llvm.org/D10867 http://reviews.llvm.org/D11678 Hope this helps. Regards, Suyog On Sat, May 28, 2016 at 4:20 AM, Rail Shafigulin via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi Shahid. > > Do you mind providing a concrete example of X86 code where an intrinsic > was added (preferrable with filenames and line numbers)? I'm having > difficulty tracking down the steps you provided. > > Any help is appreciated. > > > On Mon, Apr 4, 2016 at 9:02 PM, Sha...

...mple above the best result is from VF >=16. The draft of the patch is here: http://reviews.llvm.org/D14840 I will refine the patch later and submit it for review. thanks, Cong On Wed, Nov 18, 2015 at 2:45 PM, Cong Hou <congh at google.com> wrote: > On Mon, Nov 16, 2015 at 9:31 PM, Shahid, Asghar-ahmad > <Asghar-ahmad.Shahid at amd.com> wrote: >> Hi Cong, >> >>> -----Original Message----- >>> From: Cong Hou [mailto:congh at google.com] >>> Sent: Tuesday, November 17, 2015 12:47 AM >>> To: Shahid, Asghar-ahmad >>> Cc:...

My target has an instruction that adds up all elements in the vector and stores the result in a register. I'm trying to implement it in my compiler but I'm not sure even where to start. I did look at other targets, but they don't seem to have anything like it ( I could be wrong. My experience with LLVM is limited, so if I missed it, I'd appreciate if someone could point it out ).

Hi Shahid. Do you mind providing a concrete example of X86 code where an intrinsic was added (preferrable with filenames and line numbers)? I'm having difficulty tracking down the steps you provided. Any help is appreciated. On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad < Asghar-ahmad.Shahi...

...which breaks the intention of utilizaing vectorizable mul/recip to implement a vectorized fdiv. To fix that, one need to either combine them back or change the logic of vector type legalize. Thanks, Weiming From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of shahid shahid Sent: Thursday, September 20, 2012 10:06 PM To: Weiming Zhao; Jim Grosbach Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Proposal: New DAG node type for reciprocal operation --- On Thu, 9/20/12, Jim Grosbach <grosbach at apple.com<mailto:grosbach at apple.com>> wrote: Fro...