search for: esencia

My question is: How do I make clang to generate assembly with vector instruction for my target? The back story is: I've added a few vector instructions to my target and confirmed that they are used by running my code on the test below and using a following command: opt i.esencia.ll -S -march=esencia -mcpu=esencia -loop-vectorize | llc -mcpu=esencia -o i.esencia.s target datalayout = "E-m:e-p:32:32-i64:32-f64:32-v64:32-v128:32-a:0:32-n32" target triple = "esencia" ; Function Attrs: nounwind uwtable define i32 @main() { entry: %z = alloca <4 x i32...

I'm trying to enable/disable a target feature through clang. Here is how my target looks like // Esencia subtarget features //===----------------------------------------------------------------------===// def FeatureMul : SubtargetFeature<"mul", "HasMul", "true", "Enable hardware multiplier">; def FeatureDiv : Subtarg...

...nding is that if SDNode for such an instruction doesn't exist I have to define one. Unfortunately, I don't know how to do it. I don't even know where to start looking. Would someone care to point me in the right direction? Any help is appreciated. -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160404/0d8eed60/attachment.html>

.... I don't >> even know where to start looking. Would someone care to point me in the >> right direction? >> >> >> >> Any help is appreciated. >> >> >> >> -- >> >> Rail Shafigulin >> >> Software Engineer >> Esencia Technologies >> >> >> >> >> >> -- >> >> Rail Shafigulin >> >> Software Engineer >> Esencia Technologies >> > > > > -- > Rail Shafigulin > Software Engineer > Esencia Technologies > > On Mon, Apr 4, 20...

..., but I can't figure out how I can run it from a C code. Most of the targets have a GCCBuiltin and it looks like it is the way to execute an intrinsic from C code. However in my case there is no actual GCC built in. Any help on this is really appreciated. -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160524/f96ed2af/attachment.html>

> On Feb 1, 2016, at 16:53, Rail Shafigulin <rail at esenciatech.com> wrote: > > > > On Fri, Jan 29, 2016 at 10:03 PM, Matt Arsenault <arsenm2 at gmail.com <mailto:arsenm2 at gmail.com>> wrote: > > > On Jan 29, 2016, at 13:25, Rail Shafigulin via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm...

...to define one. Unfortunately, I don't know how to do it. I don't even > know where to start looking. Would someone care to point me in the right > direction? > > > > Any help is appreciated. > > > > -- > > Rail Shafigulin > > Software Engineer > Esencia Technologies > > > > > > -- > > Rail Shafigulin > > Software Engineer > Esencia Technologies > -- Rail Shafigulin Software Engineer Esencia Technologies On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad < Asghar-ahmad.Shahid at amd.com> wrote: >...

...R:$rD, (OpNode (i32 GPR:$rA), (i32 >> GPR:$rB)))] becomes a just a regular set. How come this is a DAG? I feel >> like I'm missing something. Would anyone be able to help with the >> explanation? >> >> -- >> Rail Shafigulin >> Software Engineer >> Esencia Technologies >> >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org >> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >> >> > -- Rail Shafigulin Software Engineer Esencia Technologi...

...it from a C code. Most of the targets have a GCCBuiltin and it looks > like it is the way to execute an intrinsic from C code. However in my case > there is no actual GCC built in. > > Any help on this is really appreciated. > > -- > Rail Shafigulin > Software Engineer > Esencia Technologies > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > > -- ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL...

> On Mar 18, 2016, at 1:37 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > >> I think you created a cycle, this is easy to do with SelectionDAG :) >> Basically SelecitonDAG will iterate until it does not see anything to change. So if you insert a transformation on a pattern A, that generates pattern B, while you have another transforma...

On Fri, Jan 29, 2016 at 11:39 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > > On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> > wrote: > >> Try visualising the DAG like this. >> >> ``` >> ---- GPR:$rA >> / >> set GPR:$rd --...

Is there a way to enable/disable target features through clang? I found this, https://github.com/avr-llvm/llvm/issues/9, but this seems to be talking about llc -mattr=+feature1,-feature2... Is there something equivalent for clang? -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160502/da652ea8/attachment.html>

...rget this new instruction (sum elements in a vector) if it is implemented as an intrinsic or the user will have to specifically invoke an instrinsic. Pardon if questions seem dumb, I'm still learning things. Any help is appreciated. On Fri, May 6, 2016 at 1:51 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > Thanks for the reply. These steps will add an instruction as an intrinsic. > Is it possible to add an actual new instruction so that a compiler could > target it during an optimization? How hard is it to do it? Is that a > realistic objective. > > Rail > &...

...represent “sum of elements in a vector” and generate your particular instruction.However, you can do it without intrinsic by pattern matching the LLVM-IRs representing “sum of elements in vector” to your particular instruction in DAGCombiner. Regards, Shahid From: Rail Shafigulin [mailto:rail at esenciatech.com] Sent: Monday, May 09, 2016 11:59 PM To: Shahid, Asghar-ahmad; llvm-dev Cc: Das, Dibyendu Subject: Re: [llvm-dev] sum elements in the vector I'm a little confused. Here is why. I was able to add a vector add instruction to my target without using any intrinsics and without adding any...

On Wed, Dec 30, 2015 at 2:48 AM, Anton Korobeynikov <anton at korobeynikov.info > wrote: > Just a side note - the assembly posted is clearly ARM, not MSP430 :) Isn't MSP430 an ARM based chip? -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151230/5617a13c/attachment.html>

On Tue, Feb 2, 2016 at 1:41 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > Let me clarify. >> >> I'm not sure I understand what you are saying. Let me post more >> information. >> >> Here is what I have defined for Escalasetflag >> >> def Escalasetflag : SDNode<"EscalaISD::SET_FLAG&quo...

...e magic flag: -debug > - read the output of SelectionDAG debugging (especially with cycles) > - matching the log to source code > What log are you talking about? > - single stepping in a debugger sometimes. > > > -- > Mehdi > > -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160318/8ff6bf5c/attachment.html>

On Fri, Mar 18, 2016 at 2:03 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > On Fri, Mar 18, 2016 at 1:53 PM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> >> On Mar 18, 2016, at 1:47 PM, Rail Shafigulin <rail at esenciatech.com> >> wrote: >> >> Yes this IR does not build or shuffle any vector....

> On Mar 18, 2016, at 1:47 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > > Yes this IR does not build or shuffle any vector. Try to write a function that takes 8 ints and a pointer to a <4xi32>, builds two vectors with the 8 ints, > > This might sound like a dumb question, but how does one build a vector of ints out of regular in...

I'm trying to clone a MachineInstr in the AsmPrinter::EmitInstruction, Here is the code: void EsenciaAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MachineFunction *MF = MI->getParent()->getParent(); MachineInstr *CloneMI = MF->CloneMachineInstr(MI); ... ... } The problem is that MF is a const and CloneMachineInstr expects a non-const. Does anybody know if there is a way...