search for: hadd

...; and check it for the first condition, because > when AVX is on, the SSE levels are all turned off (as to consider AVX > a reimplementation of all SSE levels). > > For the second condition: Does this logic works for 256-bit vectors? > I'm asking that because although the 128-bit HADDPS and the 256-bit > HADDPD have the same number of elements, their horizontal operation > behavior is different (look at AVX manual for details)! If it doesn't, > just remove the 256-bit handling for now. it's not clear whether it is correct for 256 bit operations. The AVX docs o...

The output of the avx-hadd program is 3 11 7 15 Preston -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Duncan Sands Sent: Thursday, September 22, 2011 3:14 PM To: Bruno Cardoso Lopes Cc: LLVMdev Subject: Re: [LLVMdev] Patch to synthesize x86 hadd instru...

This patch synthesizes haddps/haddpd/hsubps/hsubpd instructions from floating point additions and subtractions of appropriate vector shuffles. To do this I introduced new x86 FHADD and FHSUB opcodes. These need to be wired up somehow in the .td file to the appropriate instructions. Since I have no idea how tablegen works I...

Hi Duncan, On Wed, Sep 21, 2011 at 1:24 PM, Duncan Sands <baldrick at free.fr> wrote: > This patch synthesizes haddps/haddpd/hsubps/hsubpd instructions from > floating > point additions and subtractions of appropriate vector shuffles.  To do this > I > introduced new x86 FHADD and FHSUB opcodes.  These need to be wired up > somehow > in the .td file to the appropriate instructions.  Since I hav...

Hi Asghar-Ahmed, I saw your last ping - sorry, I'm away on vacation and back on Wednesday. Generally, I'm not sure that having both absd/hadd and sad are compatible with the discussions going on in other threads, for example my thread about min and max. Given that those two intrinsics are fairly trivial to match , I don't see the need to have two different canonical forms. James On Mon, 4 May 2015 at 07:55, Shahid, Asghar-ahmad &lt...

Hi Renato, Thanks for your response. My concern was actually this. For example, take vector type V8i16 on X86 target With llvm.sad() intrinsic: VC1 (Vector Cost) = Cost associated with "PSAD" instruction. W/ llvm.absd() and llvm.hadd() VC2 = Cost associated with "absolute diff" + "horizontal add" ( ??? ) As I will be querying with getIntrinsicCost(ID) for these two intrinsics separately, Will VC1==VC2? May be I am missing something obvious? Regards, Shahid > -----Original Message----- > From: Ren...

On 4 May 2015 at 08:37, Shahid, Asghar-ahmad <Asghar-ahmad.Shahid at amd.com> wrote: > My worry is regarding the query for cost calculation for specific SAD > instructions such as ‘psad’ (X86) or ‘usad’ (ARM) in Loop Vectorizer. Hi Shahid, The vectorizer's cost model has the ability to return different costs for the same instruction based on the arguments (scalar/vector,

...st modeling for these idioms which is complex down the lane. Pls find attached a patch regarding this which is incomplete & dirty at this moment, however, it may help in this discussion. Regards, Shahid -------------- next part -------------- A non-text attachment was scrubbed... Name: absd_hadd_sad_intrinsic.patch Type: application/octet-stream Size: 30121 bytes Desc: absd_hadd_sad_intrinsic.patch URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150501/facd5cdb/attachment.obj>

My target has an instruction that adds up all elements in the vector and stores the result in a register. I'm trying to implement it in my compiler but I'm not sure even where to start. I did look at other targets, but they don't seem to have anything like it ( I could be wrong. My experience with LLVM is limited, so if I missed it, I'd appreciate if someone could point it out ).

...e sense in general? Regards, Shahid > -----Original Message----- > From: Renato Golin [mailto:renato.golin at linaro.org] > Sent: Tuesday, May 05, 2015 8:40 PM > To: Shahid, Asghar-ahmad > Cc: James Molloy; llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics > > On 5 May 2015 at 15:41, Shahid, Asghar-ahmad <Asghar- > ahmad.Shahid at amd.com> wrote: > > With llvm.sad() intrinsic: > > VC1 (Vector Cost) = Cost associated with "PSAD" instruction. > > > > W/ llvm.absd() and llvm.hadd() > &g...

...izontal add'. Regards, Shahid > -----Original Message----- > From: Renato Golin [mailto:renato.golin at linaro.org] > Sent: Wednesday, May 06, 2015 3:22 PM > To: Shahid, Asghar-ahmad > Cc: James Molloy; llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics > > On 6 May 2015 at 06:43, Shahid, Asghar-ahmad <Asghar- > ahmad.Shahid at amd.com> wrote: > > That’s right. I agree with your *pattern vs complexity* thinking. > > > > So I would drop llvm.sad() and go ahead with the remaining two. > > > &...

...lf Of *Rail >> Shafigulin via llvm-dev >> *Sent:* Monday, April 04, 2016 11:00 PM >> *To:* Das, Dibyendu >> *Cc:* llvm-dev at lists.llvm.org >> *Subject:* Re: [llvm-dev] sum elements in the vector >> >> >> >> Thanks for the pointers. I looked at hadd instructions. They seem to do >> very similar to what I need. Unfortunately as I said before my LLVM >> experience is limited. My understanding is that when I create a new type of >> SDNode I need to specify a pattern for it, so that when LLVM is analyzing >> the code and is...

...-bounces at lists.llvm.org] *On Behalf Of *Rail > Shafigulin via llvm-dev > *Sent:* Monday, April 04, 2016 11:00 PM > *To:* Das, Dibyendu > *Cc:* llvm-dev at lists.llvm.org > *Subject:* Re: [llvm-dev] sum elements in the vector > > > > Thanks for the pointers. I looked at hadd instructions. They seem to do > very similar to what I need. Unfortunately as I said before my LLVM > experience is limited. My understanding is that when I create a new type of > SDNode I need to specify a pattern for it, so that when LLVM is analyzing > the code and is seeing a given...

...lf Of *Rail >> Shafigulin via llvm-dev >> *Sent:* Monday, April 04, 2016 11:00 PM >> *To:* Das, Dibyendu >> *Cc:* llvm-dev at lists.llvm.org >> *Subject:* Re: [llvm-dev] sum elements in the vector >> >> >> >> Thanks for the pointers. I looked at hadd instructions. They seem to do >> very similar to what I need. Unfortunately as I said before my LLVM >> experience is limited. My understanding is that when I create a new type of >> SDNode I need to specify a pattern for it, so that when LLVM is analyzing >> the code and is...

...via llvm-dev >>> *Sent:* Monday, April 04, 2016 11:00 PM >>> *To:* Das, Dibyendu >>> *Cc:* llvm-dev at lists.llvm.org >>> *Subject:* Re: [llvm-dev] sum elements in the vector >>> >>> >>> >>> Thanks for the pointers. I looked at hadd instructions. They seem to do >>> very similar to what I need. Unfortunately as I said before my LLVM >>> experience is limited. My understanding is that when I create a new type of >>> SDNode I need to specify a pattern for it, so that when LLVM is analyzing >>>...

...:llvm-dev-bounces at lists.llvm.org>] On Behalf Of Rail Shafigulin via llvm-dev Sent: Monday, April 04, 2016 11:00 PM To: Das, Dibyendu Cc: llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] sum elements in the vector Thanks for the pointers. I looked at hadd instructions. They seem to do very similar to what I need. Unfortunately as I said before my LLVM experience is limited. My understanding is that when I create a new type of SDNode I need to specify a pattern for it, so that when LLVM is analyzing the code and is seeing a given pattern it would cre...

...-bounces at lists.llvm.org] *On Behalf Of *Rail > Shafigulin via llvm-dev > *Sent:* Monday, April 04, 2016 11:00 PM > *To:* Das, Dibyendu > *Cc:* llvm-dev at lists.llvm.org > *Subject:* Re: [llvm-dev] sum elements in the vector > > > > Thanks for the pointers. I looked at hadd instructions. They seem to do > very similar to what I need. Unfortunately as I said before my LLVM > experience is limited. My understanding is that when I create a new type of > SDNode I need to specify a pattern for it, so that when LLVM is analyzing > the code and is seeing a given...

...dev-bounces at lists.llvm.org> ] On Behalf Of Rail Shafigulin via llvm-dev Sent: Monday, April 04, 2016 11:00 PM To: Das, Dibyendu Cc: llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] sum elements in the vector Thanks for the pointers. I looked at hadd instructions. They seem to do very similar to what I need. Unfortunately as I said before my LLVM experience is limited. My understanding is that when I create a new type of SDNode I need to specify a pattern for it, so that when LLVM is analyzing the code and is seeing a given pattern it would cre...

...ig, Thank you very much for your answer. I did not want to discuss exactly the semantic and name of one operation but instead raise the question "would it be beneficial to have more vector builtins?". You wrote that the compiler will recognize a pattern and replace it by __builtin_ia32_haddps when possible, but how can I be sure of that? I would have to disassemble the generated code right? It is very impractical isn'it? And it leads me to understand that each CPU target has a bank of patterns which it can recognize but wouldn't it be very similar to have advanced generic vect...

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