search for: dibyendu

We have started this. Since there are some holidays expect a small delay. Will let you know by Friday. Thx Sent from my Windows Phone ________________________________ From: Charlie Turner<mailto:charlesturner7c5 at gmail.com> Sent: ‎11/‎11/‎2015 6:34 PM To: Das, Dibyendu<mailto:Dibyendu.Das at amd.com> Cc: nrotem at apple.com<mailto:nrotem at apple.com>; llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] [RFC][SLP] Let's turn -slp-vectorize-hor on by default > I will try to get some spec cpu 2006 rate run...

----- Original Message ----- > From: "Renato Golin" <renato.golin at linaro.org> > To: "Dibyendu Das" <Dibyendu.Das at amd.com> > Cc: llvmdev at cs.uiuc.edu > Sent: Tuesday, November 4, 2014 5:23:30 AM > Subject: Re: [LLVMdev] supporting SAD in loop vectorizer > > On 4 November 2014 11:06, Das, Dibyendu <Dibyendu.Das at amd.com> wrote: > > Is there any pl...

Thanks Michael and Dibyendu for doing the experimentation and bringing this up to our attention. It might be the case what Matt described here. I will take a look at it. Farhana From: Michael Kuperstein [mailto:mkuper at google.com] Sent: Wednesday, December 14, 2016 9:56 AM To: Das, Dibyendu <Dibyendu.Das at amd.com>...

----- Original Message ----- > From: "Dibyendu Das" <Dibyendu.Das at amd.com> > To: "Hal Finkel" <hfinkel at anl.gov>, "Renato Golin" <renato.golin at linaro.org> > Cc: llvmdev at cs.uiuc.edu > Sent: Tuesday, November 4, 2014 12:15:12 PM > Subject: RE: [LLVMdev] supporting SAD in loop vecto...

----- Original Message ----- > From: "James Molloy" <james at jamesmolloy.co.uk> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "Dibyendu Das" <Dibyendu.Das at amd.com>, llvmdev at cs.uiuc.edu > Sent: Tuesday, November 11, 2014 8:21:37 AM > Subject: Re: [LLVMdev] supporting SAD in loop vectorizer > > > If you'd like to contribute support for this, look at > isHorizontalBinOp and go from there. Feel...

----- Original Message ----- > From: "Ramshankar Ramanarayanan" <Ramshankar.Ramanarayanan at amd.com> > To: "Hal Finkel" <hfinkel at anl.gov>, "Dibyendu Das" <Dibyendu.Das at amd.com> > Cc: "llvmdev at cs.uiuc.edu Mailing List" <llvmdev at cs.uiuc.edu> > Sent: Friday, October 5, 2012 11:00:39 AM > Subject: RE: [LLVMdev] LLVM Loop Vectorizer > > Perhaps we can parameterize the size of the vector while vecto...

"Das, Dibyendu" <Dibyendu.Das at amd.com> writes: > This looks to be a reasonable proposal. However native instructions > that support such masked ld/st may have a high latency ? Also, it > would be good to state some workloads where this will have a positive > impact. Any significant vec...

...cesses on x86 was, until recently, disabled by default. It's been enabled since r284779, but the cost model is very conservative, and basically assumes we're going to scalarize interleaved ops. I believe Farhana is working on improving that. Michael On Wed, Dec 14, 2016 at 8:44 AM, Das, Dibyendu <Dibyendu.Das at amd.com> wrote: > Hi Matt- > > > > Yeah I used a pretty recent llvm (post 3.9) on an x86-64 ( both AMD and > Intel ). > > > > -dibyendu > > > > *From:* Matthew Simpson [mailto:mssimpso at codeaurora.org] > *Sent:* Wednesday, Decem...

...k LLVM to generate 32-bit code - and if that would work within a 64-bit Windows application - i.e. the rest of the system will be 64-bit only the generated code will be 32-bit. I was also wondering if this would allow me to workaround the crashes due to stack unwinding problems. Thanks and Regards Dibyendu

...code to following it compiles: auto argiter = mainFunc->arg_begin(); llvm::Value *arg1 = &(*argiter); arg1->setName("obj"); As far as I can tell the first version should have worked as well. Any pointers to why the first version is now failing to compile? Thanks and Regards Dibyendu

Dear Dibyendu and Mobi, Thanks for your help! :-) I finally figure it out. The solution is really simple. I just need to generate a new bitcode file with the following command: ----- opt -mem2reg -indvars test1.bc -o test2.bc ----- Then the load/store for induction variables will be removed and replaced by PHI...

...gcc, which helps over 256AVX for several cases. The generic vector types in llvm could be put to use in opt. -----Original Message----- From: Hal Finkel [mailto:hfinkel at anl.gov] Sent: Friday, October 05, 2012 9:39 PM To: Ramanarayanan, Ramshankar Cc: llvmdev at cs.uiuc.edu Mailing List; Das, Dibyendu Subject: Re: [LLVMdev] LLVM Loop Vectorizer ----- Original Message ----- > From: "Ramshankar Ramanarayanan" <Ramshankar.Ramanarayanan at amd.com> > To: "Hal Finkel" <hfinkel at anl.gov>, "Dibyendu Das" > <Dibyendu.Das at amd.com> > Cc:...

So there's more patches in the pipeline to land, then? On Sun, Jun 25, 2017 at 10:36 PM, Das, Dibyendu <Dibyendu.Das at amd.com> wrote: > Scheduler - yes. > > Sent from my Windows Phone > ________________________________ > From: Carsten Mattner via llvm-dev > Sent: ‎6/‎25/‎2017 3:47 PM > To: llvm-dev > Subject: [llvm-dev] Zen arch in 5.0? > > Will 5.0 have schedul...

...rized (hence PSADBWs not being generated). Also, since the abs() call is already lowered to a sequence of 'icmp; neg; select' by simplifylibcalls (in -O3), we may then need to get hold of this pattern in the loop vectorizer (part of reduction analysis) and do the needful. Thoughts ? -Thx Dibyendu

...e release notes of 5.0. Please can someone describe what the change is and how I can detect whether the dump() implementation is available or not? It also seems strange that dump() implementation was removed - surely it would have been better ti stub it so that client code does not break? Regards Dibyendu

...obvious way for a client to detect whether the dump() implementation is available or not - as it does not depend upon the Release/Debug build status of the client, but how LLVM 5.0 was originally compiled. So the guards you have put are not really going to work (that is my finding anyway). Regards Dibyendu > > -----Original Message----- > From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Dibyendu Majumdar via llvm-dev > Sent: 25 September 2017 19:41 > To: llvm-dev at lists.llvm.org > Subject: [llvm-dev] Errors linking with LLVM 5.0 - dump() missing > > H...

Dear Dibyendu, Thanks for your response. :-) > If you are looking for only dependences which are inter-iteration (dependence distance != 0 ) you can do a post-pass on the ld/st addresses collected Yes, I am more interested in inter-iteration dependence. Could you provide more information or some links on...

...way due to dependencies on the C libraries etc. but on Linux/Mac OSX I never had to until now build a debug build of LLVM. As I mentioned the real problem is that the client has no way of knowing how LLVM was built - as there is no #define to flag the missing dump() implementation either. Regards Dibyendu > > -----Original Message----- > From: Dibyendu Majumdar [mailto:mobile at majumdar.org.uk] > Sent: 25 September 2017 20:57 > To: Martin J. O'Riordan <MartinO at theheart.ie> > Cc: LLVM Developers <llvm-dev at lists.llvm.org> > Subject: Re: [llvm-dev] Errors l...

...> Could you please send me your unoptimized and expected optimized code? The default implementation only contains some transformations. It would be helpful to know what you are actually trying. > Optimize Module is just a function object. > You can view the code here: https://github.com/dibyendumajumdar/ravi/blob/master/include/ravi_llvmcodegen.h https://github.com/dibyendumajumdar/ravi/blob/master/src/ravi_llvmjit.cpp Just look for USE_ORCv2_JIT The code is messy but that is because LLVM's api keeps changing from version to version, causing huge issues for users. > > On Sat,...

I will try to get some spec cpu 2006 rate runs done under -O3 -flto with and without -slp-vectorize-hor and let you know. -Thx -----Original Message----- From: nrotem at apple.com [mailto:nrotem at apple.com] Sent: Tuesday, November 10, 2015 3:33 AM To: Charlie Turner Cc: Das, Dibyendu; llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] [RFC][SLP] Let's turn -slp-vectorize-hor on by default > On Nov 9, 2015, at 9:55 AM, Charlie Turner via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I have not. I could feasibly do this, but I'm not set up to perform...