llvm dev - Jan 2016 - New register class and patterns

I've added a new register class to my target, but haven't used any of
the
new registers in any of the instructions. However when I compile llvm I get
the following error:

In SFEQ_ri: Could not infer all types in pattern

Curiously all the instructions where this error occurs are the set flag
instructions (flags like zero, less than, greater than etc).

Would anyone be able to figure out why this is happening? I can provide
more code if needed.

-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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On 1/28/2016 8:11 PM, Rail Shafigulin via llvm-dev
wrote:
>
> Would anyone be able to figure out why this is happening? I can provide
> more code if needed.
The error message should show what types have been inferred so far.

You can overcome this problem by specifying the exact type in the 
pattern, e.g. instead of Class:$Reg, have (i32 Class:$Reg).

This happens when the value can have multiple types what can be 
represented in the same register class.  For example, a 32-bit register 
could hold i32, v2i16, v4i8, etc.  When tablegen cannot figure out which 
of those it's dealing with, it will complain.

-Krzysztof

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
hosted by The Linux Foundation

On Fri, Jan 29, 2016 at 10:22 AM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 1/28/2016 8:11 PM, Rail Shafigulin via llvm-dev wrote:
>
>>
>> Would anyone be able to figure out why this is happening? I can provide
>> more code if needed.
>>
>
> The error message should show what types have been inferred so far.
>
> You can overcome this problem by specifying the exact type in the pattern,
> e.g. instead of Class:$Reg, have (i32 Class:$Reg).
>
> This happens when the value can have multiple types what can be
> represented in the same register class.  For example, a 32-bit register
> could hold i32, v2i16, v4i8, etc.  When tablegen cannot figure out which of
> those it's dealing with, it will complain.
>
> -Krzysztof
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>

I think I understand it. But looks like I have everything labelled
properly. Maybe I missed something. Here are more details:

defm SFEQ  : SF<0x0, "l.sfeq",  Escala_CC_EQ>;

multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
  def _rr : SF_RR<op2Val, asmstr, Cond>;
  def _ri : SF_RI<op2Val, asmstr, Cond>;
}

class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond>
  : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
           !strconcat(asmstr, "\t$rA, $rB"),
           [(Escalasetflag (i32 GPR:$rA), (i32 GPR:$rB), Cond)]> {
  bits<5> op2;
  bits<5> rA;
  bits<5> rB;

  let Inst{25-21} = op2;
  let Inst{20-16} = rA;
  let Inst{15-11} = rB;

  let op2 = op2Val;
}

class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
  : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
           !strconcat(asmstr, "i\t$rA, $imm"),
           [(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
  bits<5> op2;
  bits<5> rA;
  bits<16> imm;

  let Inst{25-21} = op2;
  let Inst{20-16} = rA;
  let Inst{15-0} = imm;

  let format = AFrm;
  let op2 = op2Val;
}

I would appreciate any feedback.

-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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