Displaying 6 results from an estimated 6 matches for "instrr".
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2016 Jan 29
3
New register class and patterns
...EQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
def _rr : SF_RR<op2Val, asmstr, Cond>;
def _ri : SF_RI<op2Val, asmstr, Cond>;
}
class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
!strconcat(asmstr, "\t$rA, $rB"),
[(Escalasetflag (i32 GPR:$rA), (i32 GPR:$rB), Cond)]> {
bits<5> op2;
bits<5> rA;
bits<5> rB;
let Inst{25-21} = op2;
let Inst{20-16} = rA;
let Inst{15-11} = rB;...
2016 Jan 30
1
New register class and patterns
...cala_CC_EQ>;
>
> multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
> def _rr : SF_RR<op2Val, asmstr, Cond>;
> def _ri : SF_RI<op2Val, asmstr, Cond>;
> }
>
> class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond>
> : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
> !strconcat(asmstr, "\t$rA, $rB"),
> [(Escalasetflag (i32 GPR:$rA), (i32 GPR:$rB), Cond)]> {
> bits<5> op2;
> bits<5> rA;
> bits<5> rB;
>
> let Inst{25-21} = op2;
> let I...
2016 Feb 02
2
New register class and patterns
...lticlass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
> > def _rr : SF_RR<op2Val, asmstr, Cond>;
> > def _ri : SF_RI<op2Val, asmstr, Cond>;
> > }
> >
> > class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond>
> > : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
> > !strconcat(asmstr, "\t$rA, $rB"),
> > [(Escalasetflag (i32 GPR:$rA), (i32 GPR:$rB), Cond)]> {
> > bits<5> op2;
> > bits<5> rA;
> > bits<5> rB;
> >
> > l...
2016 Jan 29
2
New register class and patterns
I've added a new register class to my target, but haven't used any of the
new registers in any of the instructions. However when I compile llvm I get
the following error:
In SFEQ_ri: Could not infer all types in pattern
Curiously all the instructions where this error occurs are the set flag
instructions (flags like zero, less than, greater than etc).
Would anyone be able to figure out
2016 Feb 05
3
New register class and patterns
...t;"Esencia", [i1,i32], 32, (add SR)> {
let CopyCost = -1; // Don't allow copying of special purpose registers.
let isAllocatable = 0;
}
Then I changed an instruction class to return an explicit value
class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond> :
InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
!strconcat(asmstr, "\t$rA, $rB"),
[(set SPR:$rC, (Esenciasetflag (i32 GPR:$rA), (i32
GPR:$rB), Cond))]> {
bits<5> op2;
bits<5> rA;
bits<5> rB;
let Inst{25-21} = op2;
let Inst{20-16} = r...
2016 Feb 04
2
New register class and patterns
It does have an output register, it's just an implicit flag register. It
still has a DAG output. I'm not sure if the allocatable bit matters at this
point for selection purposes, but it does later. Not adding a type to the
register class can also be problematic (e.g. a flag register should have i1
added to regTypes for its class).
-Matt
>
Does LLVM make an assumption that there is an