Displaying 14 results from an estimated 14 matches for "_ri".
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2017 Dec 03
2
5.0.1-rc2 has been tagged
...e across an llvm bug when compiling some testcases that 64-bit
> immediates are silently truncated into 32-bit and then packed into
> BPF_JMP | BPF_K encoding. This caused comparison with wrong value.
>
> This bug looks to be introduced by r308080 (llvm 5.0). The
> Select_Ri pattern is
> supposed to be lowered into J*_Ri while the latter only support 32-bit
> immediate encoding, therefore Select_Ri should have similar immediate
> predicate check as what J*_Ri are doing.
>
> The bug is fixed by
> git-svn-id: https://llvm.org/svn/llv...
2016 Jan 29
3
New register class and patterns
...and it. But looks like I have everything labelled
properly. Maybe I missed something. Here are more details:
defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
def _rr : SF_RR<op2Val, asmstr, Cond>;
def _ri : SF_RI<op2Val, asmstr, Cond>;
}
class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
!strconcat(asmstr, "\t$rA, $rB"),
[(Escalasetflag (i32 GPR:$rA), (i32 GPR:$rB), Cond)]> {
bits<5>...
2017 Nov 30
9
5.0.1-rc2 has been tagged
Hi,
I've tagged the 5.0.1-rc2 release, go ahead and start testing and report
your results.
-Tom
2016 Jan 30
1
New register class and patterns
...everything labelled properly. Maybe I missed something. Here are more details:
>
> defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
>
> multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
> def _rr : SF_RR<op2Val, asmstr, Cond>;
> def _ri : SF_RI<op2Val, asmstr, Cond>;
> }
>
> class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond>
> : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
> !strconcat(asmstr, "\t$rA, $rB"),
> [(Escalasetflag (i32 GPR:$rA), (i32 GPR:$rB...
2012 Apr 19
2
[LLVMdev] Tablegen to match a literal in an instruction
...de OpNode, RegisterClass dReg,
RegisterClass sReg0, RegisterClass sReg1, Operand lit>
{
def _rr: ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1),
!strconcat(op.Text, " $dst, $src0, $src1"),
[(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
def _ri : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, lit:$src1),
"and $dst, $src0, $src1"),
[(set dReg:$dst, (OpNode sReg0:$src0, imm:$src1))]>;
}
multiclass BinaryOpMCInt<SDNode OpNode> {
defm _i32 : BinaryOp<OpNode, GPRI32, GPRI32, GPRI32, i32imm>;
}
def...
2012 Apr 19
3
[LLVMdev] Tablegen to match a literal in an instruction
...de OpNode, RegisterClass dReg,
RegisterClass sReg0, RegisterClass sReg1, Operand lit>
{
def _rr: ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1),
!strconcat(op.Text, " $dst, $src0, $src1"),
[(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
def _ri : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, lit:$src1),
"and $dst, $src0, $src1"),
[(set dReg:$dst, (OpNode sReg0:$src0, imm:$src1))]>;
}
multiclass BinaryOpMCInt<SDNode OpNode> {
defm _i32 : BinaryOp<OpNode, GPRI32, GPRI32, GPRI32, i32imm>;
}
def...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...> RegisterClass sReg0, RegisterClass sReg1, Operand lit>
> {
> def _rr: ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1),
> !strconcat(op.Text, " $dst, $src0, $src1"),
> [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
> def _ri : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, lit:$src1),
> "and $dst, $src0, $src1"),
> [(set dReg:$dst, (OpNode sReg0:$src0, imm:$src1))]>;
>
> }
> multiclass BinaryOpMCInt<SDNode OpNode> {
> defm _i32 : BinaryOp<OpNode, GPRI32, GP...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...> RegisterClass sReg0, RegisterClass sReg1, Operand lit>
> {
> def _rr: ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1),
> !strconcat(op.Text, " $dst, $src0, $src1"),
> [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
> def _ri : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, lit:$src1),
> "and $dst, $src0, $src1"),
> [(set dReg:$dst, (OpNode sReg0:$src0, imm:$src1))]>;
>
> }
> multiclass BinaryOpMCInt<SDNode OpNode> {
> defm _i32 : BinaryOp<OpNode, GPRI32, GP...
2016 Feb 02
2
New register class and patterns
.... Maybe I missed something. Here are more details:
> >
> > defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
> >
> > multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
> > def _rr : SF_RR<op2Val, asmstr, Cond>;
> > def _ri : SF_RI<op2Val, asmstr, Cond>;
> > }
> >
> > class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond>
> > : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
> > !strconcat(asmstr, "\t$rA, $rB"),
> > [(Escalasetfla...
2016 Jan 29
2
New register class and patterns
I've added a new register class to my target, but haven't used any of the
new registers in any of the instructions. However when I compile llvm I get
the following error:
In SFEQ_ri: Could not infer all types in pattern
Curiously all the instructions where this error occurs are the set flag
instructions (flags like zero, less than, greater than etc).
Would anyone be able to figure out why this is happening? I can provide
more code if needed.
--
Rail Shafigulin
Software Eng...
2016 Feb 04
2
New register class and patterns
...ofile<0, 3, [SDTCisSameAs<0, 1>]>;
def Escalatflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag,
[SDNPOutGlue]>;
def Escala_CC_EQ : PatLeaf<(imm),
[{return (N->getZExtValue() == ISD::SETEQ);}]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),
[(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
bits<5> op2;
bits<5> rA;
bits<16> i...
2016 Feb 04
2
New register class and patterns
...I'm repeating some code for reference.
Any help is appreciated.
def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag,
[SDNPOutGlue]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),
[(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
bits<5> op2;
bits<5> rA;
bits<16> i...
2016 Jun 02
2
BPF backend with vector operations - error "Could not infer all types in, pattern!"
...backend):
>> def MSA128W: RegisterClass<"BPF", [v2i64, v2f64], 128,
>> (sequence "W%u", 0, 31)>;
>> in order to support vector for example, ADD operations, I get the following error when
>> building llc:
>> JEQ_ri: (BPFbrcc i64:i64:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$imm,
>> (imm:{i64:v4i32})<<P:Predicate_BPF_CC_EQ>>, (bb:Other):$BrDst)
>> Included from ~/LLVM/llvm38Nov2016/llvm/lib/Target/BPF/BPF.td:14:
>> ~/LLVM/llvm38Nov2016/llvm/lib/Target/BPF/BP...
2016 Feb 19
3
Failure to match a DAG after a minor pattern change in a custom Target
...weak, I'd appreciate any
help on this. For that matter, any opportunity to learn about LLVM is
welcomed. Original code, modified code as well as the error are provided
below. I can provide more if needed. There were two changes made. One in
the definition of SDT_EsenciaSetFlag and another in SF_RI class
(specifically in its DAG pattern).
Any help is appreciated.
========================= Orignal Code =====================================
def SDT_EsenciaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG"...