llvm dev - Feb 2016 - New register class and patterns

>
>
>
>
> def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
>                                           SDTCisVec<1>,
>                                           SDTCisSameAs<2, 1>]>;
>
> This is confusing to me. This tells me that there is 1 result but and 2
> operands. But then it says that operands 2 and 1 are of the same type,
> SDTCisSameAs<2, 1>. Given that operand numbering starts at 0, how can
there
> be operands 2 and 1?
>
>
> The results are numbered starting from 0. In this case with 1 result, 0 is
> the output operand, and 1 and 2 are the inputs.
>
>
>
> Based on the previous answer my understanding is that LLVM is complaining
> because it doesn't know what register to use. What is unclear to me is
why?
> I already had 2 register classes before and everything was working. All
> I've done is that I had added an extra class. After that LLVM started
to
> complain. And this is what puzzles me.
>
> Did you add a register class for a special condition register? Did you set
> it as isAllocatable = 0?
>
I think I'm slowly getting it. To answer your question, no I did not set
isAllocaable = 0 for the new register class. But I'm still confused.
Original instruction does not have an output register. It sets a flag in
the special purpose register. So why creating a new register class would
cause a problem? In other words, since there is no output register, why
would LLVM start complaining. Below I'm repeating some code for reference.
Any help is appreciated.

def SDT_EscalaSetFlag      : SDTypeProfile<0, 3, [SDTCisSameAs<0,
1>]>;

def Esenciasetflag     : SDNode<"EsenciaISD::SET_FLAG",
SDT_EsenciaSetFlag,
                             [SDNPOutGlue]>;

class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
  : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
           !strconcat(asmstr, "i\t$rA, $imm"),
           [(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
  bits<5> op2;
  bits<5> rA;
  bits<16> imm;

  let Inst{25-21} = op2;
  let Inst{20-16} = rA;
  let Inst{15-0} = imm;

  let format = AFrm;
  let op2 = op2Val;
}

-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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On 02/03/2016 06:17 PM, Rail Shafigulin via llvm-dev
wrote:
> I think I'm slowly getting it. To answer your question, no I did not 
> set isAllocaable = 0 for the new register class. But I'm still 
> confused. Original instruction does not have an output register. It 
> sets a flag in the special purpose register. So why creating a new 
> register class would cause a problem? In other words, since there is 
> no output register, why would LLVM start complaining. Below I'm 
> repeating some code for reference. Any help is appreciated.
It does have an output register, it's just an implicit flag register. It 
still has a DAG output. I'm not sure if the allocatable bit matters at 
this point for selection purposes, but it does later. Not adding a type 
to the register class can also be problematic (e.g. a flag register 
should have i1 added to regTypes for its class).

-Matt

It does have an output register, it's just an implicit flag register. It
still has a DAG output. I'm not sure if the allocatable bit matters at this
point for selection purposes, but it does later. Not adding a type to the
register class can also be problematic (e.g. a flag register should have i1
added to regTypes for its class).

-Matt
>
Does LLVM make an assumption that there is an implicit register output if
there are no outputs given to the pattern? I'm also curious about how did
LLVM know that an output of this instruction was setting a flag in a
special purpose register rather than a GPR? When I look at the DAG pattern
for the instruction, (Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond), I
can't find anything saying that it sets a flag in the special purpose
register.

I'm reposting code for convenience.

def SDT_EscalaSetFlag      : SDTypeProfile<0, 3, [SDTCisSameAs<0,
1>]>;

def Escalatflag     : SDNode<"EscalaISD::SET_FLAG",
SDT_EscalaSetFlag,
                             [SDNPOutGlue]>;

def Escala_CC_EQ  : PatLeaf<(imm),
                  [{return (N->getZExtValue() == ISD::SETEQ);}]>;

class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
  : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
           !strconcat(asmstr, "i\t$rA, $imm"),
           [(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
  bits<5> op2;
  bits<5> rA;
  bits<16> imm;

  let Inst{25-21} = op2;
  let Inst{20-16} = rA;
  let Inst{15-0} = imm;

  let format = AFrm;
  let op2 = op2Val;
}

multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
  def _rr : SF_RR<op2Val, asmstr, Cond>;
  def _ri : SF_RI<op2Val, asmstr, Cond>;
}

defm SFEQ  : SF<0x0, "l.sfeq",  Escala_CC_EQ>;


-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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