search for: patleaf

...ck to this older thread. Again, because of i64immSExt32 I receive TableGen error "Could not infer all types in, pattern!" (exact details written below). So far I'm not able to generate selection code with TableGen for the ADD_r* instructions, etc: def i64immSExt32 : PatLeaf<(imm), [{return isInt<32>(N->getSExtValue()); }]>; As in the case of https://groups.google.com/forum/#!topic/llvm-dev/LfltBGG9ru0 : "It seems that defining a new register class changes how the tblgen infers the types in the DAG patterns. So what is the r...

Hello. I've tried to add some simple arithmetic vector operations to the BPF backend available in the LLVM repo. Because I added in BPFRegisterInfo.td another RegisterClass (taken from the Mips backend): def MSA128W: RegisterClass<"BPF", [v2i64, v2f64], 128, (sequence "W%u", 0, 31)>; in order to support vector for example, ADD

...ists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details: defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>; multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> { def _rr : SF_RR<op2Val, asmstr, Cond>; def _ri : SF_RI<op2Val, asmstr, Cond>; } class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB), !strconcat(asmstr, "\t$rA, $rB"), [(Esc...

On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote: > You need to specify sub-register == super-register, idx relationship. > See X86RegisterInfo.td: > > def x86_subreg_8bit : PatLeaf<(i32 1)>; > def x86_subreg_16bit : PatLeaf<(i32 2)>; > def x86_subreg_32bit : PatLeaf<(i32 3)>; > > def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, > R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], > [AL, CL,...

On Dec 17, 2009, at 3:10 PM, David Greene wrote: > I'm working on debugging AVX shuffles and I ran into an interesting > problem. > > The current isSHUFPMask predicate in X86ISelLowering needs to be > generalized to operate on 128-bit or 256-bit masks. There are > probably lots of other things to change too (LowerVECTOR_SHUFFLE_4wide, > etc.) but I'll worry about

Hello, David > Can you expand on this with an example?  There seems to be an awful lot of > shuffle patterns and predicates in PPCInstrAltivec.td.  What do you mean by, > "Canonicalize to byte ops?"  Can you walk me through how that works with > Altivec? The basic idea is quite simple - lower everything to vNi8 and write all the patterns using only these types. -- With

On Dec 17, 2009, at 4:12 PM, David Greene wrote: > On Thursday 17 December 2009 18:04, Anton Korobeynikov wrote: >> Hello, David >> >>> Can you expand on this with an example? There seems to be an awful lot >>> of shuffle patterns and predicates in PPCInstrAltivec.td. What do you >>> mean by, "Canonicalize to byte ops?" Can you walk me

...or something similar), how would I express that extra argument in the .td file? Right now we do: SHUFP_shuffle_mask:$src3 to add the predicate to check the 3rd (mask) operand for conformance to something SHUFPS/D can handle. Is there some way currently to add another "argument" to the PatLeaf invocation? -Dave

There can also be other “problems" like this one: http://reviews.llvm.org/D6946 <http://reviews.llvm.org/D6946> - Matthias > On Apr 20, 2015, at 1:44 PM, Tim Northover <t.p.northover at gmail.com> wrote: > >> The DAG combiner also performs the undefined shift -> undef though, so it >> should still be OK > > DAG combiner doesn't really run to

On Thursday 17 December 2009 17:16, Nate Begeman wrote: > David, this is probably the wrong approach, based on the accreted awfulness > of the X86 shuffle lowering code, Ha! I have no issue believing this statement. :) > The correct approach is probably a rewrite based around what > AltiVec does: Canonicalize to byte ops, and write all the patterns once > rather than having to

On Thursday 17 December 2009 18:04, Anton Korobeynikov wrote: > Hello, David > > > Can you expand on this with an example?  There seems to be an awful lot > > of shuffle patterns and predicates in PPCInstrAltivec.td.  What do you > > mean by, "Canonicalize to byte ops?"  Can you walk me through how that > > works with Altivec? > > The basic idea is

You need to specify sub-register == super-register, idx relationship. See X86RegisterInfo.td: def x86_subreg_8bit : PatLeaf<(i32 1)>; def x86_subreg_16bit : PatLeaf<(i32 2)>; def x86_subreg_32bit : PatLeaf<(i32 3)>; def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], [AL, CL, DL, BL, SPL, BPL, SIL, DIL,...

On Oct 15, 2008, at 5:29 AM, sanjiv gupta wrote: > On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote: >> You need to specify sub-register == super-register, idx relationship. >> See X86RegisterInfo.td: >> >> def x86_subreg_8bit : PatLeaf<(i32 1)>; >> def x86_subreg_16bit : PatLeaf<(i32 2)>; >> def x86_subreg_32bit : PatLeaf<(i32 3)>; >> >> def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, >> R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], >>...

On Thu, 2008-10-02 at 11:19 -0700, Evan Cheng wrote: > > On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote: > > > What’s the value produced by an INSERT_SUBREG node? Is it a chain? > > > No, insert_subreg returns a value: > > > v1 = insert_subreg v2, v3, idx > > > v1 and v2 will have the same type, e.g. i16, and v3 must have a >

...> wrote: > > > > I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details: > > defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>; > > multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> { > def _rr : SF_RR<op2Val, asmstr, Cond>; > def _ri : SF_RI<op2Val, asmstr, Cond>; > } > > class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond> > : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB), > !strconcat(asmstr, "...

...l purpose register. I'm reposting code for convenience. def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; def Escalatflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag, [SDNPOutGlue]>; def Escala_CC_EQ : PatLeaf<(imm), [{return (N->getZExtValue() == ISD::SETEQ);}]>; class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm), !strconcat(asmstr, "i\t$rA, $imm"), [(Escalasetflag (i32 GPR...

...ny help is appreciated. def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag, [SDNPOutGlue]>; class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm), !strconcat(asmstr, "i\t$rA, $imm"), [(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> { bits<5> op2; bits<5> rA; bits<16> imm; let Inst{25-21} = op2; let Inst{20-16}...

I've added a new register class to my target, but haven't used any of the new registers in any of the instructions. However when I compile llvm I get the following error: In SFEQ_ri: Could not infer all types in pattern Curiously all the instructions where this error occurs are the set flag instructions (flags like zero, less than, greater than etc). Would anyone be able to figure out

Hi all, I want to match addition with 16bit integers. So I define a pattern fragment as follows: def simm16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; Now I am confused between (add R32:$dst, simm16:$im) and (add R32:$dst, (i32 simm16:$im)). Do both of them match the same pattern? Are they equivalent? If not what is the difference? I am also confused as to how ValueTypes relate...

...= Orignal Code ===================================== def SDT_EsenciaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag, [SDNPOutGlue]>; def Esencia_CC_LT : PatLeaf<(imm), [{return (N->getZExtValue() == ISD::SETLT);}]>; class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm), !strconcat(asmstr, "i\t$rA, $imm"), [(Esenciasetflag (i32 G...