Displaying 8 results from an estimated 8 matches for "sf_rr".
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sf_ri
2016 Jan 29
3
New register class and patterns
...istinfo/llvm-dev
>
I think I understand it. But looks like I have everything labelled
properly. Maybe I missed something. Here are more details:
defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
def _rr : SF_RR<op2Val, asmstr, Cond>;
def _ri : SF_RI<op2Val, asmstr, Cond>;
}
class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
!strconcat(asmstr, "\t$rA, $rB"),
[(Escalasetflag (i32 GPR:$rA), (i3...
2016 Jan 30
1
New register class and patterns
...think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details:
>
> defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
>
> multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
> def _rr : SF_RR<op2Val, asmstr, Cond>;
> def _ri : SF_RI<op2Val, asmstr, Cond>;
> }
>
> class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond>
> : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
> !strconcat(asmstr, "\t$rA, $rB"),
>...
2016 Feb 02
2
New register class and patterns
...But looks like I have everything labelled properly. Maybe I missed something. Here are more details:
> >
> > defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
> >
> > multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
> > def _rr : SF_RR<op2Val, asmstr, Cond>;
> > def _ri : SF_RI<op2Val, asmstr, Cond>;
> > }
> >
> > class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond>
> > : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
> > !strconcat(asmstr, "\t$rA...
2016 Jan 29
2
New register class and patterns
I've added a new register class to my target, but haven't used any of the
new registers in any of the instructions. However when I compile llvm I get
the following error:
In SFEQ_ri: Could not infer all types in pattern
Curiously all the instructions where this error occurs are the set flag
instructions (flags like zero, less than, greater than etc).
Would anyone be able to figure out
2016 Feb 04
2
New register class and patterns
...A), immSExt16:$imm, Cond)]> {
bits<5> op2;
bits<5> rA;
bits<16> imm;
let Inst{25-21} = op2;
let Inst{20-16} = rA;
let Inst{15-0} = imm;
let format = AFrm;
let op2 = op2Val;
}
multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
def _rr : SF_RR<op2Val, asmstr, Cond>;
def _ri : SF_RI<op2Val, asmstr, Cond>;
}
defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
--
Rail Shafigulin
Software Engineer
Esencia Technologies
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2016 Feb 05
3
New register class and patterns
...ur advice and added i1 as a type for my SPR
def SPR : RegisterClass<"Esencia", [i1,i32], 32, (add SR)> {
let CopyCost = -1; // Don't allow copying of special purpose registers.
let isAllocatable = 0;
}
Then I changed an instruction class to return an explicit value
class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond> :
InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
!strconcat(asmstr, "\t$rA, $rB"),
[(set SPR:$rC, (Esenciasetflag (i32 GPR:$rA), (i32
GPR:$rB), Cond))]> {
bits<5> op2;
bits<5>...
2016 Feb 04
2
New register class and patterns
>
>
>
>
> def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
> SDTCisVec<1>,
> SDTCisSameAs<2, 1>]>;
>
> This is confusing to me. This tells me that there is 1 result but and 2
> operands. But then it says that operands 2 and 1 are of the same type,
2016 Feb 19
3
Failure to match a DAG after a minor pattern change in a custom Target
...Ext16:$imm), (i32 Cond)))]> {
bits<5> op2;
bits<5> rA;
bits<16> imm;
let Inst{25-21} = op2;
let Inst{20-16} = rA;
let Inst{15-0} = imm;
let format = AFrm;
let op2 = op2Val;
}
multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
def _rr : SF_RR<op2Val, asmstr, Cond>;
def _ri : SF_RI<op2Val, asmstr, Cond>;
}
defm SFLTS : SF<0xc, "l.sflts", Esencia_CC_LT>;
========================= Orignal Match Result
=====================================
Selecting: 0x2ebfa78: glue = EsenciaISD::SET_FLAG 0x2ebee18, 0x2ebef2...