search for: op2

...w in R and i need some help. Please, ¿do you know a function how can process cross tables for many variables and show the result in one table who look like this?: +----------------------------------------------------+ |------------------ | X variable | |----------------- | Xop1 | Xop2 | Xop3|.....| +----------------------------------------------------+ |Yvar1 | Total | %row..........................| | | Op1 | %row..........................| | | Op2 | %row..........................| |+---------------------------------------------------+ |Yvar2 | Op1 | %row.....

....llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details: defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>; multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> { def _rr : SF_RR<op2Val, asmstr, Cond>; def _ri : SF_RI<op2Val, asmstr, Cond>; } class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB), !strconcat(asmstr, "\t$rA, $...

...nt *MUL_LOHI for my processor. My processor has mulxss (e.g.) that gives the 32 high bits of a 64 bit multiply. I tried this in ios2ISelDAGToDAG.cpp: /// Mul/Div with two results case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { SDValue Op1 = Node->getOperand(0); SDValue Op2 = Node->getOperand(1); AddToISelQueue(Op1); AddToISelQueue(Op2); unsigned Op; Op = (Opcode == ISD::UMUL_LOHI ? Nios2::MULxu : Nios2::MULx); SDNode *Hi = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2); SDNode *Lo = CurDAG->getTargetNode(Nios2::MUL,...

Our architecture has 1-bit boolean predicate registers. I've defined comparison def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; But then I end up having the following bug: Code %0 = zext i8 %data to i32 %1 = zext i16 %crc to i32 %2 = xor i32 %1, %0 %3 = and i32 %2, 1 %4 = icmp eq i32 %3, 0 which compares the lowest bits of the 2...

The langref says for the 'add' instruction: Syntax: <result> = add <ty> <op1>, <op2> ; yields {ty}:result <result> = nuw add <ty> <op1>, <op2> ; yields {ty}:result <result> = nsw add <ty> <op1>, <op2> ; yields {ty}:result <result> = nuw nsw add <ty> <op1>, <op2> ; yields {ty}:resul...

...'no-overflow'. This is the updated solution devised in the discussion: http://lists.llvm.org/pipermail/llvm-dev/2017-October/118257.html The proposed keywords: "nof" stands for 'no-overflow' Syntax: <result> = sdiv nof <ty> <op1>, <op2> ; yields ty:result <result> = udiv nof <ty> <op1>, <op2> ; yields ty:result Overview: If the keyword is present, the compiler can assume no zero values in the denominator. Moreover, for sdiv the division MIN_INT / -1 is prohibited. Otherwise, undefined behavio...

...(snip) I've ran the good and bad bitcode files for a more compact example (attached) through llvm-bcanalyzer and diff: --- bad.xml 2013-01-09 22:57:58.691131492 +0400 +++ good.xml 2013-01-09 22:58:04.153133734 +0400 ... irrelevant ... <STRUCT_NAME abbrevid=7 op0=105 op1=46 op2=78 op3=105 op4=108 op5=67 op6=108 op7=97 op8=115 op9=115/> <STRUCT_NAMED abbrevid=8 op0=0 op1=0 op2=6/> <POINTER abbrevid=4 op0=7 op1=0/> - <STRUCT_ANON abbrevid=6 op0=0 op1=0 op2=6/> </TYPE_BLOCK_ID> <GLOBALVAR abbrevid=4 op0=8 op1=0 op2=2 op3=...

...ct ~ group1 + ids + time, data = d1) ftable(op1, row.vars=c(1,3)) ## For group2 d2 <- aggregate(cbind(x1, x2) ~ group2 + ids + time, data = df, sum) d2$l_pct <- with(d2, ave(x1, list(group2, time), FUN = function(x) round(prop.table(x) * 100, 1) ) ) op2 <- xtabs(l_pct ~ group2 + ids + time, data = d2) ftable(op2, row.vars=c(1,3)) ## and for group3... ## To have a more flexible solution I wrote this function: myfun <- function(xdf, xvar) { fo1 <- "cbind(x1, x2) ~ " fo2 <- paste(fo1, xvar, "+ ids + time", sep=&...

On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > Our architecture has 1-bit boolean predicate registers. > > I've defined comparison > > > def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; > > > > > But then I end up having the following bug: > > > Code > > > %0 = zext i8 %data to i32 > %1 = zext i16 %crc to i32 > %2 = xor i32 %1, %0 > %3 = and i32 %2, 1...

...:500), state2 = (201:700) ) with data that partially overlap in terms of values. I want to minimize the assessment error of each state by using this function: err.th.scalar <- function(threshold, data){ state1 <- data$state1 state2 <- data$state2 op1l <- length(state1) op2l <- length(state2) op1.err <- sum(state1 <= threshold)/op1l op2.err <- sum(state2 >= threshold)/op2l total.err <- (op1.err + op2.err) return(total.err) } SO I'm trying to minimize the total error. This Total Error should be a U shape essentially. I'm usi...

Hello. I've managed to create a bitcode file (attached; also available at [1]) which produces a series of identical errors when verified: | Global variable initializer type does not match global variable type! | %i.NilClass* @nil When ran through llvm-dis and recompiled, through, it verifies successfully. If I disassemble it one more time, the result is identical to the first

...e.startswith("bt") + && !(Name.endswith("b") || Name.endswith("w") || Name.endswith("l") || Name.endswith("q")) + && Operands.size() == 3) { + X86Operand &Op1 = *(X86Operand*)Operands.begin()[1]; + X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; + + if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) && + Op2.isMem() && isa<MCConstantExpr>(Op2.Mem.Disp)) { + int64_t Given_imm = cast<MCConstantExpr>(Op1.getImm())->getValue(); + int64_t Given_mem...

...m-dev at lists.llvm.org> wrote: > > > > I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details: > > defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>; > > multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> { > def _rr : SF_RR<op2Val, asmstr, Cond>; > def _ri : SF_RI<op2Val, asmstr, Cond>; > } > > class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond> > : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB), >...

I've added a new register class to my target, but haven't used any of the new registers in any of the instructions. However when I compile llvm I get the following error: In SFEQ_ri: Could not infer all types in pattern Curiously all the instructions where this error occurs are the set flag instructions (flags like zero, less than, greater than etc). Would anyone be able to figure out

...eikki Kultala wrote: >>>> >>>>> Our architecture has 1-bit boolean predicate registers. >>>>> >>>>> I've defined comparison >>>>> >>>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; >>>>> >>>>> But then I end up having the following bug: >>>>> >>>>> Code >>>>> >>>>> %0 = zext i8 %data to i32 >>>>&g...

On Thu, Sep 11, 2008 at 4:31 PM, Arnold Schwaighofer <arnold.schwaighofer at gmail.com> wrote: > Tail calls through function pointers should work.If not please send a testcase. > > I just added the two examples from the bug (1392) that calls for true > tail call support. They work on my machine (-tailcallopt needs to be > enabled) ;) > > That would be commit 56127. >

...sSameAs<0, 1>]>; def Escalatflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag, [SDNPOutGlue]>; def Escala_CC_EQ : PatLeaf<(imm), [{return (N->getZExtValue() == ISD::SETEQ);}]>; class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm), !strconcat(asmstr, "i\t$rA, $imm"), [(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> { bits<5> op2; bits<5> rA; bits<16> imm; let Inst{25-21...

...e code for reference. Any help is appreciated. def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag, [SDNPOutGlue]>; class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm), !strconcat(asmstr, "i\t$rA, $imm"), [(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> { bits<5> op2; bits<5> rA; bits<16> imm; let Inst{25-21...

...es that there cannot be no "intra bundle dependencies", otherwise those instructions could not be executed in parallel in the reality. For example, looking at your example of a bundle with "intra-bundle dependencies": ------------------------- | r0 = op1 r1, r2 | | r3 = op2 r0<kill>, #c | ------------------------- In case of a static VLIW target the semantics of this instruction is that these two "RISC instructions are executed in parallel, period". Thus, the first instruction cannot depend on the latter (or the other way around) but op2 reads the old...

...ode->getValueType(0) ; SDValue ChainIn = Node->getOperand(0); SDValue Zero = CurDAG->getCopyFromReg(ChainIn, DL, Mips::ZERO, MVT::i32); SDValue op0 = Node->getOperand(2); SDValue op1 = Node->getOperand(3); SDValue op2= Node->getOperand(4); SDValue op3 = Node->getOperand(5); SDValue Ops[]= { op0, op1, op2, op3, Zero, ChainIn }; SDNode *Result = CurDAG->getMachineNode(Mips::BWT_DROP_RESULT, SDLoc(Node), ReturnValueVT, Ops);...