Displaying 9 results from an estimated 9 matches for "op2val".
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2016 Jan 29
3
New register class and patterns
....llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
I think I understand it. But looks like I have everything labelled
properly. Maybe I missed something. Here are more details:
defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
def _rr : SF_RR<op2Val, asmstr, Cond>;
def _ri : SF_RI<op2Val, asmstr, Cond>;
}
class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
!strconcat(asmstr, "\t$rA, $rB&...
2016 Jan 30
1
New register class and patterns
...m-dev at lists.llvm.org> wrote:
>
>
>
> I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details:
>
> defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
>
> multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
> def _rr : SF_RR<op2Val, asmstr, Cond>;
> def _ri : SF_RI<op2Val, asmstr, Cond>;
> }
>
> class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond>
> : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
> !...
2016 Jan 29
2
New register class and patterns
I've added a new register class to my target, but haven't used any of the
new registers in any of the instructions. However when I compile llvm I get
the following error:
In SFEQ_ri: Could not infer all types in pattern
Curiously all the instructions where this error occurs are the set flag
instructions (flags like zero, less than, greater than etc).
Would anyone be able to figure out
2016 Feb 04
2
New register class and patterns
...sSameAs<0, 1>]>;
def Escalatflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag,
[SDNPOutGlue]>;
def Escala_CC_EQ : PatLeaf<(imm),
[{return (N->getZExtValue() == ISD::SETEQ);}]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),
[(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
bits<5> op2;
bits<5> rA;
bits<16> imm;
let Inst{25-21} =...
2016 Feb 04
2
New register class and patterns
...e code for reference.
Any help is appreciated.
def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag,
[SDNPOutGlue]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),
[(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
bits<5> op2;
bits<5> rA;
bits<16> imm;
let Inst{25-21} =...
2016 Feb 02
2
New register class and patterns
...> >
> >
> >
> > I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details:
> >
> > defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
> >
> > multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
> > def _rr : SF_RR<op2Val, asmstr, Cond>;
> > def _ri : SF_RI<op2Val, asmstr, Cond>;
> > }
> >
> > class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond>
> > : InstRR<0x9, (outs), (ins GPR:$rA...
2016 Feb 19
3
Failure to match a DAG after a minor pattern change in a custom Target
...lt;0, 1>]>;
def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag,
[SDNPOutGlue]>;
def Esencia_CC_LT : PatLeaf<(imm),
[{return (N->getZExtValue() == ISD::SETLT);}]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),
[(Esenciasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
bits<5> op2;
bits<5> rA;
bits<16> imm;
let Inst{25-21}...
2016 Feb 05
3
New register class and patterns
...as a type for my SPR
def SPR : RegisterClass<"Esencia", [i1,i32], 32, (add SR)> {
let CopyCost = -1; // Don't allow copying of special purpose registers.
let isAllocatable = 0;
}
Then I changed an instruction class to return an explicit value
class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond> :
InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
!strconcat(asmstr, "\t$rA, $rB"),
[(set SPR:$rC, (Esenciasetflag (i32 GPR:$rA), (i32
GPR:$rB), Cond))]> {
bits<5> op2;
bits<5> rA;
bits<5> rB;...
2016 Feb 03
2
New register class and patterns
On Tue, Feb 2, 2016 at 8:42 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>
> On Feb 2, 2016, at 16:52, Rail Shafigulin <rail at esenciatech.com> wrote:
>
> def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
>
>
> I think for setting an implicit register, you still need to have 1 result
> here.
>
> If you look at