search for: asmstr

llvm/lib/Target/X86/X86InstrInfo.td: class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> : Instruction { .... dag OperandList = ops; string AsmString = AsmStr; } def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}">; I cannot find any document on initializing the 'dag' type variabl...

The macro $src, $dest used in Instruction::AsmString must be "declared" in Instruction::OperandList, right? $$ has special meaning? On 5/6/05, Chris Lattner <sabre at nondot.org> wrote: > On Fri, 6 May 2005, Tzu-Chien Chiu wrote: > > llvm/lib/Target/X86/X86InstrInfo.td: > > class X86Inst<bits<8> opcod, Fo...

On Fri, 6 May 2005, Tzu-Chien Chiu wrote: > llvm/lib/Target/X86/X86InstrInfo.td: > class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string > AsmStr> : Instruction { > .... > dag OperandList = ops; > string AsmString = AsmStr; > } > > def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), > "mov{l} {$src, $dst|$dst, $src}">; > > I cannot find any document on init...

...http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details: defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>; multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> { def _rr : SF_RR<op2Val, asmstr, Cond>; def _ri : SF_RI<op2Val, asmstr, Cond>; } class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB), !strconcat(asmstr, "\t$rA, $rB"),...

...n Silva wrote: > I think you're missing the template args for `FRRR16_ins` in the first > argument. The switch in TGParser::ParseType() doesn't cover the case > of types with template args though... which makes me wonder what is > going on inside of TableGen to make `I.f` and `I.AsmString` valid... > > --Sean Silva > > On Mon, Jul 2, 2012 at 8:07 PM, reed kotler<rkotler at mips.com> wrote: >> I've filed the following bug. Maybe I'm doing something stupid here or >> maybe someone knows of a workaround. >> >> The following fragment...

...ntation which has the same problem. class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, !cast<FRRR16_ins>(I).OutOperandList, !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } def foo: ArithLogicRTest16<"AdduRxRyRz16", add, 1>; I think that the problem has to do wit...

class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, InstrItinClass itin> : // ... This class has template args. You don't specify them in the first template arg of class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ... --Sean Silva On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at...

...e some modifications to our code generator that will produce better code, but require adding new patterns. What I am trying to do is take a register/register pattern and change it to a register/immediate. So for example, I have this pattern: class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace = "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit ha...

...et checked into main source). The problem is that I should be able to pass parameters: I.OutOperandList, I.InOperandList But instead, I must back substitute what I know the values of these are. (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz) class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, InstrItinClass itin> : FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), !strconcat(asmstr, "\t$rz, $rx, $ry"), pattern, itin>; class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit...

...SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), // !cast<FRRR16_ins>(I).OutOperandList, // !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } On 07/05/2012 03:11 PM, reed kotler wrote: > I think that what I did originally should have worked and t...

...llvm.org> wrote: > > > > I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details: > > defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>; > > multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> { > def _rr : SF_RR<op2Val, asmstr, Cond>; > def _ri : SF_RI<op2Val, asmstr, Cond>; > } > > class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond> > : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB), > !strconcat(asmst...

...e some modifications to our code generator that will produce better code, but require adding new patterns. What I am trying to do is take a register/register pattern and change it to a register/immediate. So for example, I have this pattern: class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace = "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit ha...

...ng a new target into LLVM. However there is a assembler for that target and I just want LLVM to generate assembly. I read the document "Writing an LLVM Backend". I am wondering to know whether I can ignore the Inst field in the following example: class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { field bits<32> Inst; let Namespace = "SP"; bits<2> op; let Inst{31-30} = op; dag OutOperandList = outs; dag InOperandList = ins; let AsmString = asmstr; let Pattern = pattern; } And define the instruction class o...

...o initialize(set up) register attributes when we define an instruction? like if a register is defined like this: " class SC_Register<bits<8> register_num, REG_FLAG SC_X, REG_FLAG SC_Y, REG_FLAG SC_Z, REG_FLAG SC_W, string asmstr> : Register<asmstr> { let HWEncoding{7-0} = register_num; // register_num let HWEncoding{8} = SC_X; let HWEncoding{9} = SC_Y; ….. }” can I set up the input/ouput register flags like this? or some other way in codegen to make the register flags are set up b...

...to our code generator that will produce better code, but require adding new patterns. > > What I am trying to do is take a register/register pattern and change it to a register/immediate. > So for example, I have this pattern: > class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> > : Instruction { > let Namespace = "AMDIL"; > dag OutOperandList = outs; > dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); &g...

...S, $rB", IntSimple, 1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; Okay, so rA, rS, and rB are register operands. The TableGen classes are defined as: 315 class XForm_base_r3xo_swapped 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 317 InstrItinClass itin> 318 : I<opcode, OOL, IOL, asmstr, itin> { 319 bits<5> A; 320 bits<5> RST; 321 bits<5> B; 322 323 bit RC = 0; // set by isDOT 324 325 let Inst{6-10} = RST; 326 let Inst{11-15} = A; 327 let Inst{16-20} = B; 328 let In...

I think you're missing the template args for `FRRR16_ins` in the first argument. The switch in TGParser::ParseType() doesn't cover the case of types with template args though... which makes me wonder what is going on inside of TableGen to make `I.f` and `I.AsmString` valid... --Sean Silva On Mon, Jul 2, 2012 at 8:07 PM, reed kotler <rkotler at mips.com> wrote: > I've filed the following bug. Maybe I'm doing something stupid here or > maybe someone knows of a workaround. > > The following fragment from mips16 (not yet checked into...

...(outs), (ins MEMri:$addr, IntRegs:$src), "st $src, [$addr]", [(store IntRegs:$src, ADDRri:$addr)]>; F3_2 and it's superclasses are defined as follows: class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { bits<13> simm13; let op = opVal; let op3 = op3val; let Inst{13} = 1; // i field = 1 let Inst{12-0} = simm13; } class F3<dag outs, dag ins, string asmstr, list<dag> pattern>...

...to our code generator that will produce better code, but require adding new patterns. > > What I am trying to do is take a register/register pattern and change it to a register/immediate. > So for example, I have this pattern: > class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> > : Instruction { > let Namespace = "AMDIL"; > dag OutOperandList = outs; > dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); &g...

...RC:$rS, GPRC:$rB))]>; > > > > Okay, so rA, rS, and rB are register operands. > > > > The TableGen classes are defined as: > > > > 315 class XForm_base_r3xo_swapped > > 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string > asmstr, > > 317 InstrItinClass itin> > > 318 : I<opcode, OOL, IOL, asmstr, itin> { > > 319 bits<5> A; > > 320 bits<5> RST; > > 321 bits<5> B; > > 322 > > 323 bit RC = 0; // set by isDOT > > > > 324 > &...