Displaying 7 results from an estimated 7 matches for "sfeq".
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2016 Jan 29
3
New register class and patterns
..._________________________________
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> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
I think I understand it. But looks like I have everything labelled
properly. Maybe I missed something. Here are more details:
defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
def _rr : SF_RR<op2Val, asmstr, Cond>;
def _ri : SF_RI<op2Val, asmstr, Cond>;
}
class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond>
: In...
2016 Feb 05
3
New register class and patterns
>
> No, this would have to be a void side effecting instruction which is a bit
> different.
What do you mean by "void side effecting instruction"? I'm not sure I
fully understand what you mean.
The flag register is an implicit register added to the selected
> MachineInstr's operands.
Is this something that is always done by LLVM? Is it me who is telling to
LLVM
2016 Jan 30
1
New register class and patterns
> On Jan 29, 2016, at 13:25, Rail Shafigulin via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
>
>
> I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details:
>
> defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
>
> multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
> def _rr : SF_RR<op2Val, asmstr, Cond>;
> def _ri : SF_RI<op2Val, asmstr, Cond>;
> }
>
> class SF_RR<bits<5> op2Val, str...
2016 Feb 02
2
New register class and patterns
...Shafigulin via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
> >
> >
> >
> > I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details:
> >
> > defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
> >
> > multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
> > def _rr : SF_RR<op2Val, asmstr, Cond>;
> > def _ri : SF_RI<op2Val, asmstr, Cond>;
> > }
> >
> > class S...
2016 Jan 29
2
New register class and patterns
I've added a new register class to my target, but haven't used any of the
new registers in any of the instructions. However when I compile llvm I get
the following error:
In SFEQ_ri: Could not infer all types in pattern
Curiously all the instructions where this error occurs are the set flag
instructions (flags like zero, less than, greater than etc).
Would anyone be able to figure out why this is happening? I can provide
more code if needed.
--
Rail Shafigulin
Software...
2016 Feb 04
2
New register class and patterns
...imm;
let Inst{25-21} = op2;
let Inst{20-16} = rA;
let Inst{15-0} = imm;
let format = AFrm;
let op2 = op2Val;
}
multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
def _rr : SF_RR<op2Val, asmstr, Cond>;
def _ri : SF_RI<op2Val, asmstr, Cond>;
}
defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
--
Rail Shafigulin
Software Engineer
Esencia Technologies
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2016 Feb 04
2
New register class and patterns
>
>
>
>
> def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
> SDTCisVec<1>,
> SDTCisSameAs<2, 1>]>;
>
> This is confusing to me. This tells me that there is 1 result but and 2
> operands. But then it says that operands 2 and 1 are of the same type,