llvm dev - May 2012 - [LLVMdev] Register coalescing (Subregs and SuperRegs)

On May 14, 2012, at 4:09 PM, "Pranav Bhandarkar" <pranavb at
codeaurora.org> wrote:
> Hi,
> 
> Consider this MI code from the hexagon backend.
> ------------------------------------------------------------------
> 16B             %vreg0<def> = COPY %R0<kill>; IntRegs:%vreg0
> 32B             %vreg1<def> = LDriw %vreg0, 0; mem:LD4[%a]
> IntRegs:%vreg1,%vreg0
> 48B             %vreg2<def> = LDriw_indexed %vreg0<kill>, 4;
> mem:LD4[%add.ptr] IntRegs:%vreg2,%vreg0
> 64B             %vreg7<def> = COMBINE_rr %vreg2<kill>,
%vreg1<kill>;
> DoubleRegs:%vreg7 IntRegs:%vreg2,%vreg1 
> 80B             %D0<def> = COPY %vreg7<kill>; DoubleRegs:%vreg7
> ------------------------------------------------------------------
> LDriw and LDriw_indexed load  32 -bit words. So %vreg1 and %vreg2 are both
> 32-bit virtual registers. Hexagon has register pairs and even-odd registers
> can be paired to form 64-bit registers.
> For instance, physical registers R0 and R1 can form the register pair
R1:R0.
> Similarly R3:R2 with the odd number register holding the higher 32 bits and
> the even numbered register holds the lower 32-bits.
> 
> Consider now the COMBINE_rr instruction
> ------------------------------------------------------------------
> %vreg7<def> = COMBINE_rr %vreg2<kill>, %vreg1<kill>;
DoubleRegs:%vreg7
> IntRegs:%vreg2,%vreg1
> ------------------------------------------------------------------
> 
> It creates a 64bit vreg by making %vreg2 the higher word and %vreg1 the
> lower word in the DoubleReg.
> 
> The optimization opportunity here is that if %vreg2 and %vreg1 are
allocated
> the right registers (odd for %vreg2 and even for %vreg1) then the
COMBINE_rr
> instruction can be made redundant.
Your COMBINE_rr instruction does exactly what the target-independent
REG_SEQUENCE instruction does. The important difference is that REG_SEQUENCE is
recognized by the coalescer to do exactly what you need.

You simply need to generate REG_SEQUENCE instead of COMBINE_rr. Look at the ARM
target for examples.

/jakob