search for: superreg

...R3:R2 i.e %D0 in the hexagon backend. The question is this possible in the current setup of the Reg. Coalescer and the Reg. Allocator ? Or is there some target hook that'll help me inform the Register coalescer or the allocator ? @Jakob: I noticed your commit last week regarding TRI::getCommonSuperRegClass(). Can that have a role to play here? FWIW, the relevant patterns for COMBINE_rr are shown below. ------------------------------------------------------------------ // Combine. let isPredicable = 1, neverHasSideEffects = 1 in def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst),...

On May 14, 2012, at 4:09 PM, "Pranav Bhandarkar" <pranavb at codeaurora.org> wrote: > Hi, > > Consider this MI code from the hexagon backend. > ------------------------------------------------------------------ > 16B %vreg0<def> = COPY %R0<kill>; IntRegs:%vreg0 > 32B %vreg1<def> = LDriw %vreg0, 0; mem:LD4[%a] >

Hi, Recently on trunk, the ovlaps list for a register got a dual entry on my target, which caused the RA to crash. Reg Subreg1 Subreg b Subreg2 Subreg b I have a register with two subregs that have subreg b in common. This causes the SuperReg to appear twice in the ovelaps list for Subreg b. As this causes a register allocator to crasch (it evicts a register, and then inremenets the *AliasI, but the data structure is then not ready to be re-used, so a dual entry is not expected here), I suggest that TableGen makes the overlaps list a s...

Hello, David > How does ${dst:subreg32} work? This is just modifier provided to asmprinting code. Here, it seems, 16 bit register is passed to asmprinter, but it sees modifier and grabs 32-bit superreg. > Can one do the same for sources? Yes, this is just modifier for printing, nothing more... > Is it preferable to use the source modifier or write an EXTRACT_SUBREG > pattern explicitly? It depends what you're want to do. But I guess you need to model subreg access properly... --...

What's the value produced by an INSERT_SUBREG node? Is it a chain? Can I use to set a superreg of i16 type with two i8 values, and use the supperreg as an operand somewhere else? - Sanjiv -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20081002/f07bc88c/attachment.html>

...y an INSERT_SUBREG node? Is it a chain? > > > No, insert_subreg returns a value: > > > v1 = insert_subreg v2, v3, idx > > > v1 and v2 will have the same type, e.g. i16, and v3 must have a > sub-register type, e.g. i8. > > > > > Can I use to set a superreg of i16 type with two i8 values, and use > > the supperreg as an operand somewhere else? > > > Suppose you want to use a pair of i8 v1, v2 to create a i16 v3. The > way to do it is: > > > v4 = insert_subreg implicit_def, v1, 0 > v3 = insert_subreg v4,...

On Tuesday 24 November 2009 14:12, Anton Korobeynikov wrote: > Hello, David > > > How does ${dst:subreg32} work? > > This is just modifier provided to asmprinting code. Here, it seems, 16 > bit register is passed to asmprinter, but it sees modifier and grabs > 32-bit superreg. > > > Can one do the same for sources? > > Yes, this is just modifier for printing, nothing more... > > > Is it preferable to use the source modifier or write an EXTRACT_SUBREG > > pattern explicitly? > > It depends what you're want to do. But I guess you ne...

Hi, I have a MachineInstr that writes to a subreg, but clobbers the superreg. How should I BuildMI this instruction? I try to do a IMPLICIT_DEF super_reg and then write to a subreg of that super register , but it gets DCE:ed. Is there a way to express this clobbering of a superregister? thanks, Jonas -------------- next part -------------- An HT...

..., > > Recently on trunk, the ovlaps list for a register got a dual entry on my target, which caused the RA to crash. > > Reg > Subreg1 > Subreg b > Subreg2 > Subreg b > > I have a register with two subregs that have subreg b in common. This causes the SuperReg to appear twice in the ovelaps list for Subreg b This should be fixed in r156629. /jakob -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120511/571b7cff/attachment.html>

..., Sanjiv.Gupta at microchip.com wrote: > What’s the value produced by an INSERT_SUBREG node? Is it a chain? No, insert_subreg returns a value: v1 = insert_subreg v2, v3, idx v1 and v2 will have the same type, e.g. i16, and v3 must have a sub- register type, e.g. i8. > Can I use to set a superreg of i16 type with two i8 values, and use > the supperreg as an operand somewhere else? Suppose you want to use a pair of i8 v1, v2 to create a i16 v3. The way to do it is: v4 = insert_subreg implicit_def, v1, 0 v3 = insert_subreg v4, v2, 1 Evan > > - Sanjiv > ____...

...t;> >> >> No, insert_subreg returns a value: >> >> >> v1 = insert_subreg v2, v3, idx >> >> >> v1 and v2 will have the same type, e.g. i16, and v3 must have a >> sub-register type, e.g. i8. >> >>> >>> Can I use to set a superreg of i16 type with two i8 values, and use >>> the supperreg as an operand somewhere else? >> >> >> Suppose you want to use a pair of i8 v1, v2 to create a i16 v3. The >> way to do it is: >> >> >> v4 = insert_subreg implicit_def, v1, 0 >> v3 = i...

...t know if it will be helpful or not, to see what the live interval and reg allocator are doing. I'm having trouble debugging this, any idea on where I might want to look? Another question is how do I influence the spill costs? I want to make live in's infinitely expensive to spill, so any superreg or super-super-reg of the live in never gets allocated. Thanks, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110701/702ffcda/attachment.html> -------------- next part -------------- An embedded...

Hi Quentin, Let me clarify if I understood this correctly. If the accesses (writes and reads) to sub-registers are expressed always as sub-registers of the super-register register class (e.g., SuperReg.sub1;), then the spilling decision is for the super register. But, if the accesses are in terms of the register class of the sub-registers directly (SubReg;), then the spilling decision will be for the sub-register. So if we forced before register allocation all sub-register accesses to be ac...

...gned SubIdx) { // Pick the register class of the subregister TargetRegisterInfo::regclass_iterator I = TRC->subregclasses_begin() + SubIdx-1; assert(I < TRC->subregclasses_end() && "Invalid subregister index for register class"); return *I; } /// getSuperRegisterRegClass - Returns the register class of a superreg A whose /// "SubIdx"'th sub-register class is the specified register class and whose /// type matches the specified type. static const TargetRegisterClass* getSuperRegisterRegClass(const TargetRegisterClass *TRC,...

...ere I might want to look? It's hard to tell without knowing your target. Why does the allocator think there are no free registers in your register class? > Another question is how do I influence the spill costs? I want to make live in's > > infinitely expensive to spill, so any superreg or super-super-reg of the live in > never gets allocated. It's not clear what you mean here. Spill costs are assigned to virtual registers, and virtual registers don't have sub- or super-registers. If you mean linear scan's emergency spilling of physical registers, that should neve...

...mede at ece.ubc.ca> wrote: >> >> Hi Quentin, >> >> Let me clarify if I understood this correctly. >> >> If the accesses (writes and reads) to sub-registers are expressed >> always as sub-registers of the super-register register class (e.g., >> SuperReg.sub1;), then the spilling decision is for the super register. >> >> But, if the accesses are in terms of the register class of the >> sub-registers directly (SubReg;), then the spilling decision will be >> for the sub-register. >> >> >> So if we forced...

...t;>> >>> Hi Quentin, >>> >>> Let me clarify if I understood this correctly. >>> >>> If the accesses (writes and reads) to sub-registers are expressed >>> always as sub-registers of the super-register register class (e.g., >>> SuperReg.sub1;), then the spilling decision is for the super >>> register. >>> >>> But, if the accesses are in terms of the register class of the >>> sub-registers directly (SubReg;), then the spilling decision will be >>> for the sub-register. >>>...

...n that is failing! If I don't use sub-registers, then I don't have this problem, but then I really can't specify that one register class is a subclass of another. Another question is how do I influence the spill costs? I want to make live in's infinitely expensive to spill, so any superreg or super-super-reg of the live in never gets allocated. It's not clear what you mean here. Spill costs are assigned to virtual registers, and virtual registers don't have sub- or super-registers. If you mean linear scan's emergency spilling of physical registers, that should never hap...

...On Jan 30, 2018, at 10:21 AM, ahmede <ahmede at ece.ubc.ca> wrote: > > Hi Quentin, > > Let me clarify if I understood this correctly. > > If the accesses (writes and reads) to sub-registers are expressed always as sub-registers of the super-register register class (e.g., SuperReg.sub1;), then the spilling decision is for the super register. > > But, if the accesses are in terms of the register class of the sub-registers directly (SubReg;), then the spilling decision will be for the sub-register. > > > So if we forced before register allocation all sub-regi...

...;>>> >>>> v1 = insert_subreg v2, v3, idx >>>> >>>> >>>> v1 and v2 will have the same type, e.g. i16, and v3 must have a >>>> sub-register type, e.g. i8. >>>> >>>>> >>>>> Can I use to set a superreg of i16 type with two i8 values, and >>>>> use >>>>> the supperreg as an operand somewhere else? >>>> >>>> >>>> Suppose you want to use a pair of i8 v1, v2 to create a i16 v3. The >>>> way to do it is: >>>> &...