Displaying 5 results from an estimated 5 matches for "ldriw_indexed".
2012 Apr 27
0
[LLVMdev] MemRefs in a Load Instruction
...f: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1,
>
> s11_2ExtPred:$offset1)))),
> (i32 32))),
> (i64 (zextloadi32
ADDRriS11_2:$src2)))),
> (i64 (COMBINE_rr (LDriw_indexed IntRegs:$src1,
> s11_2ExtPred:$offset1),
> (LDriw
ADDRriS11_2:$src2)))>;
> ******************************
I had to modify the above pattern where in the LDriw (the second load in the
COMBINE_rr) is changed to LDriw_indexed similar to the f...
2012 Apr 26
2
[LLVMdev] MemRefs in a Load Instruction
...********************
def: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1,
s11_2ExtPred:$offset1)))),
(i32 32))),
(i64 (zextloadi32 ADDRriS11_2:$src2)))),
(i64 (COMBINE_rr (LDriw_indexed IntRegs:$src1,
s11_2ExtPred:$offset1),
(LDriw ADDRriS11_2:$src2)))>;
******************************
Without getting into too much detail, all that the pattern is doing is
combining the results of two 32 bit loads into a 64 bit value.
The two loads...
2012 May 14
0
[LLVMdev] Register coalescing (Subregs and SuperRegs)
...is MI code from the hexagon backend.
------------------------------------------------------------------
16B %vreg0<def> = COPY %R0<kill>; IntRegs:%vreg0
32B %vreg1<def> = LDriw %vreg0, 0;
mem:LD4[%a],IntRegs:%vreg1,%vreg0
48B %vreg2<def> = LDriw_indexed %vreg0<kill>, 4;
mem:LD4[%add.ptr] IntRegs:%vreg2,%vreg0
64B %vreg7<def> = COMBINE_rr %vreg2<kill>, %vreg1<kill>;
DoubleRegs:%vreg7 IntRegs:%vreg2,%vreg1
80B %D0<def> = COPY %vreg7<kill>; DoubleRegs:%vreg7
---------------------------...
2012 May 14
0
[LLVMdev] Register coalescing (Subregs and SuperRegs)
...on backend.
> ------------------------------------------------------------------
> 16B %vreg0<def> = COPY %R0<kill>; IntRegs:%vreg0
> 32B %vreg1<def> = LDriw %vreg0, 0; mem:LD4[%a]
> IntRegs:%vreg1,%vreg0
> 48B %vreg2<def> = LDriw_indexed %vreg0<kill>, 4;
> mem:LD4[%add.ptr] IntRegs:%vreg2,%vreg0
> 64B %vreg7<def> = COMBINE_rr %vreg2<kill>, %vreg1<kill>;
> DoubleRegs:%vreg7 IntRegs:%vreg2,%vreg1
> 80B %D0<def> = COPY %vreg7<kill>; DoubleRegs:%vreg7
> --...
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...R10,R11] in
>> -def LDriw_pred : LDInst<(outs PredRegs:$dst),
>> +def LDriw_pred : LDInst2<(outs PredRegs:$dst),
>> (ins MEMri:$addr),
>> "Error; should not emit",
>> []>;
>> @@ -1435,19 +1435,19 @@ def LDriw_indexed : LDInst<(outs IntRegs:$dst),
>> s11_2ImmPred:$offset)))]>;
>>
>> let mayLoad = 1, neverHasSideEffects = 1 in
>> -def LDriw_GP : LDInst<(outs IntRegs:$dst),
>> +def LDriw_GP : LDInst2<(outs IntRegs:$dst),
>&...