Displaying 20 results from an estimated 114 matches for "intregs".
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...>> (ins globaladdress:$global),
>> "$dst=memd(#$global)",
>> []>;
>>
>> let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
>> -def POST_LDrid : LDInstPI<(outs DoubleRegs:$dst, IntRegs:$dst2),
>> +def POST_LDrid : LDInst2PI<(outs DoubleRegs:$dst, IntRegs:$dst2),
>> (ins IntRegs:$src1, s4Imm:$offset),
>> "$dst = memd($src1++#$offset)",
>> [],
>> @@ -895,64 +895,64 @@ def POST_LDrid : LDInstPI<(...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...t here – look at this – before phi elimination this code looks much more sane:
>
> # *** IR Dump After Live Variable Analysis ***:
> # Machine code for function push: SSA
> Function Live Outs: %R0
>
> BB#0: derived from LLVM BB %entry
> %vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5
> %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4
> Successors according to CFG: BB#1
>
> BB#1: derived from LLVM BB %for.cond
> Predecessors according to CFG: BB#0 BB#1
> %vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>;...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...str = top->first;
}
If the loop never iterates, "top" will have garbage in it. If it iterates
even once, it will presumably have valid pointer. Bad, but perfectly valid
code.
In SSA it looked like this:
BB#0: derived from LLVM BB %entry
%vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<Dummy def.
%vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4
Successors according to CFG: BB#1
BB#1: derived from LLVM BB %for.cond
Predec...
2019 Jun 30
6
[hexagon][PowerPC] code regression (sub-optimal code) on LLVM 9 when generating hardware loops, and the "llvm.uadd" intrinsic.
...ware Loops” pass to recognise a hardware loop pattern, resulting in sub-optimal code, specially compared with what LLVM 7.0 produces.
The code (excerpt) just before the Hexagon Hardware Loops pass on LLVM 9 is this:
bb.5:
; predecessors: %bb.1
successors: %bb.3(0x80000000); %bb.3(100.00%)
%8:intregs = A2_tfrsi -100
J2_jump %bb.3, implicit-def $pc
bb.3.while.body:
; predecessors: %bb.3, %bb.5
successors: %bb.4(0x04000000), %bb.3(0x7c000000); %bb.4(3.12%), %bb.3(96.88%)
%0:intregs = PHI %8:intregs, %bb.5, %3:intregs, %bb.3
%1:intregs = PHI %7:intregs, %bb.5, %5:intregs, %bb.3
%2:intr...
2012 Jun 14
1
[LLVMdev] Assert in live update from MI scheduler.
...st;
> }
>
> If the loop never iterates, “top” will have garbage in it. If it iterates even once, it will presumably have valid pointer. Bad, but perfectly valid code.
>
> In SSA it looked like this:
> BB#0: derived from LLVM BB %entry
> %vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<Dummy def.
> %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4
> Successors according to CFG: BB#1
>
> BB#1: derived from LLVM BB %for....
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...You are probably right here - look at this - before phi elimination this
code looks much more sane:
# *** IR Dump After Live Variable Analysis ***:
# Machine code for function push: SSA
Function Live Outs: %R0
BB#0: derived from LLVM BB %entry
%vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5
%vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4
Successors according to CFG: BB#1
BB#1: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
%vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>;
IntRegs:%vreg0,%vreg4,%...
2019 Jul 01
0
[hexagon][PowerPC] code regression (sub-optimal code) on LLVM 9 when generating hardware loops, and the "llvm.uadd" intrinsic.
...ware Loops” pass to recognise a hardware loop pattern, resulting in sub-optimal code, specially compared with what LLVM 7.0 produces.
The code (excerpt) just before the Hexagon Hardware Loops pass on LLVM 9 is this:
bb.5:
; predecessors: %bb.1
successors: %bb.3(0x80000000); %bb.3(100.00%)
%8:intregs = A2_tfrsi -100
J2_jump %bb.3, implicit-def $pc
bb.3.while.body:
; predecessors: %bb.3, %bb.5
successors: %bb.4(0x04000000), %bb.3(0x7c000000); %bb.4(3.12%), %bb.3(96.88%)
%0:intregs = PHI %8:intregs, %bb.5, %3:intregs, %bb.3
%1:intregs = PHI %7:intregs, %bb.5, %5:intregs, %bb.3
%2:int...
2012 Jun 19
2
[LLVMdev] How to define macros in a tablegen file?
Hi,
I was wondering if there is a way to specify macros to help shorten
rewriting patterns like these:
def : Pat <(v4i8 (mul (v4i8 IntRegs:$a), (v4i8 IntRegs:$b))),
(v4i8
(VTRUNEHB
(v4i16
(VTRUNEWH
(v2i32
(VMPYH
(v2i16
(EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$a))), subreg_hireg)),
(v2i16
(EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$b))), subreg_hireg)))),
(v2i32...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...mple... When parsing (BU order) this
> instruction:
>
> SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
>
> The %vreg10<def> never inserted to VRegDefs, so with next instruction:
>
> SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
>
> Anti dep on %vreg10 is never created.
Thanks for the detailed explanation! My understanding is that COPY %vreg10<kill> is illegal because is has no reaching def on all paths (LDriw is the only def).
Now, the (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) check...
2010 Dec 15
2
[LLVMdev] Optimization passes break machine instructions on new backend
...te
the Machine code being initially correct:
# Machine code for function func:
Function Live Ins: %R0 in reg%16384, %R1 in reg%16385, %R2 in reg%16386, %R3
in reg%16387
Function Live Outs: %R0
BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %R2 %R3
%reg16387<def> = COPY %R3; IntRegs:%reg16387
%reg16386<def> = COPY %R2; IntRegs:%reg16386
%reg16385<def> = COPY %R1; IntRegs:%reg16385
%reg16384<def> = COPY %R0; IntRegs:%reg16384
%reg16390<def> = MOVE %reg16386; IntRegs:%reg16390,16386
%reg16388<def> = CMPrr %reg...
2012 Sep 18
0
[LLVMdev] liveness assertion problem in llc
On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote:
> I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some
2012 Sep 18
2
[LLVMdev] liveness assertion problem in llc
...e informative backtrace):
# *** IR Dump Before Calculate spill weights ***:
# Machine code for function CGA_kernel_read: Post SSA
Function Live Ins: %P0 in %vreg5, %P1 in %vreg6
Function Live Outs: %P15
0B BB#0: derived from LLVM BB %entry
Live Ins: %P0 %P1
16B %vreg6<def> = COPY %P1; IntRegs:%vreg6
48B %vreg8<def> = MOV32ri <ga:@fifo>, pred:%noreg; IntRegs:%vreg8 dbg:../src/getbits.c:46:1
64B %vreg9<def> = LDUBri %vreg8, 1, pred:%noreg; mem:LD1[getelementptr inbounds (%struct.FIFO* @fifo, i32 0, i32 1)] IntRegs:%vreg9,%vreg8 dbg:../src/getbits.c:46:1
80B %vreg10<...
2013 Apr 05
3
[LLVMdev] Generate addi 40, r3 instruction
I want to generate the instruction like
addi 40, r3 ! i.e. r3 = r3 + 40
The format i wrote is
def ADDI : F1<opcode, (outs IntRegs:$dst), (ins IntRegs:$dst, i32imm:$imm)
"addi $imm, $dst",
[(set $IntRegs:$dst, (add $IntRegs:$dst, i32imm:$c))]
but it is not compiling.
what should be the format.
vikram
--
View this message in context: http://llvm.1065342.n5.nabble.com...
2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
...p;& "moveAllOperandsFrom
broke liveness."' failed.
The code being scheduled (function "push") is trivial:
# Machine code for function push: Post SSA
Function Live Outs: %R0
0B BB#0: derived from LLVM BB %entry
16B %vreg9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
Successors according to CFG: BB#1
48B BB#1: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
96B %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
Int...
2012 Aug 28
5
[LLVMdev] Assert in LiveInterval update
...a region:
R2 = [0B,48r:0)[352r,416r:5)...
R3 = [0B,48r:0)[368r,416r:5)...
R4 = [0B,32r:0)[384r,416r:4)...
R5 = [0B,32r:0)[400r,416r:4)...
I schedule the following instruction (48B):
0B BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %D1 %D2
8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
12B %vreg30<def> = LDriw <fi#-1>, 0;
mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
IntRegs:%vreg31
24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;...
2007 Oct 19
0
[LLVMdev] Adding address registers to back-end
...compiler generates the some code as before, but that seems to
> be ok, because I haven't used ptr_rc yet.
>
> 4) I changed the address mode MEMri:
>
> def MEMri : Operand<iPTR> {
> let PrintMethod = "printMemOperand";
> // was: let MIOperandInfo = (ops IntRegs, i32imm);
> let MIOperandInfo = (ops ptr_rc, i32imm);
> }
>
> for the C code int c; void f(void) { c = 4711; } I get the error
> message:
>
> Register class of operand and regclass of use don't agree!
> Operand = 0
> Op->Val = 0x42b08d60: i32 = SETHIi 0x42b08d00...
2007 Oct 19
2
[LLVMdev] Adding address registers to back-end
...) to my InstrInfo class
The compiler generates the some code as before, but that seems to
be ok, because I haven't used ptr_rc yet.
4) I changed the address mode MEMri:
def MEMri : Operand<iPTR> {
let PrintMethod = "printMemOperand";
// was: let MIOperandInfo = (ops IntRegs, i32imm);
let MIOperandInfo = (ops ptr_rc, i32imm);
}
for the C code int c; void f(void) { c = 4711; } I get the error
message:
Register class of operand and regclass of use don't agree!
Operand = 0
Op->Val = 0x42b08d60: i32 = SETHIi 0x42b08d00
MI = STri %reg1026
VReg = 1026
VRe...
2012 Jan 18
1
[LLVMdev] Pattern matching in a SelectionDAG
...BA : BranchSP<0b1000, (ins brtarget:$dst),
"ba $dst",
[(br bb:$dst)]>;
The pattern that is to be matched is simply (br bb: $dst). Based on this, I
would have expected the pattern for an add instruction to look somehow like
this: (add IntRegs:$b, IntRegs:$c). But in reality, it looks like this:
(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))
What is this "set" thing all about? It doesn't seem to be a node in the
graph, as the pattern is also matched in a graph in which the add node's
ancestor is, say, a mul node. So...
2012 Jun 19
0
[LLVMdev] How to define macros in a tablegen file?
...Tuesday, June 19, 2012 3:39 PM
> To: llvmdev at cs.uiuc.edu
> Subject: [LLVMdev] How to define macros in a tablegen file?
>
> Hi,
>
> I was wondering if there is a way to specify macros to help shorten
> rewriting patterns like these:
>
> def : Pat <(v4i8 (mul (v4i8 IntRegs:$a), (v4i8 IntRegs:$b))),
> (v4i8
> (VTRUNEHB
> (v4i16
> (VTRUNEWH
> (v2i32
> (VMPYH
> (v2i16
> (EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$a))),
> subreg_hireg)),
> (v2i16
> (EXTRACT_SUBREG (v4i16 (VSXT...
2012 Aug 30
0
[LLVMdev] Assert in LiveInterval update
...r,416r:5)...
> R4 = [0B,32r:0)[384r,416r:4)...
> R5 = [0B,32r:0)[400r,416r:4)...
>
> I schedule the following instruction (48B):
>
> 0B BB#0: derived from LLVM BB %entry
> Live Ins: %R0 %R1 %D1 %D2
> 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
> 12B %vreg30<def> = LDriw <fi#-1>, 0;
> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
> IntRegs:%vreg31
> 24B %vreg26<def> = COPY %R0<kill>;...