Displaying 6 results from an estimated 6 matches for "combine_rr".
2012 May 14
0
[LLVMdev] Register coalescing (Subregs and SuperRegs)
...%vreg0<def> = COPY %R0<kill>; IntRegs:%vreg0
32B %vreg1<def> = LDriw %vreg0, 0;
mem:LD4[%a],IntRegs:%vreg1,%vreg0
48B %vreg2<def> = LDriw_indexed %vreg0<kill>, 4;
mem:LD4[%add.ptr] IntRegs:%vreg2,%vreg0
64B %vreg7<def> = COMBINE_rr %vreg2<kill>, %vreg1<kill>;
DoubleRegs:%vreg7 IntRegs:%vreg2,%vreg1
80B %D0<def> = COPY %vreg7<kill>; DoubleRegs:%vreg7
------------------------------------------------------------------
LDriw and LDriw_indexed load 32 -bit words. So %vreg1 and %vreg2 are...
2012 Apr 26
2
[LLVMdev] MemRefs in a Load Instruction
...********************************
def: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1,
s11_2ExtPred:$offset1)))),
(i32 32))),
(i64 (zextloadi32 ADDRriS11_2:$src2)))),
(i64 (COMBINE_rr (LDriw_indexed IntRegs:$src1,
s11_2ExtPred:$offset1),
(LDriw ADDRriS11_2:$src2)))>;
******************************
Without getting into too much detail, all that the pattern is doing is
combining the results of two 32 bit loads into a 64 bit value....
2012 Apr 27
0
[LLVMdev] MemRefs in a Load Instruction
...gt;
> def: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1,
>
> s11_2ExtPred:$offset1)))),
> (i32 32))),
> (i64 (zextloadi32
ADDRriS11_2:$src2)))),
> (i64 (COMBINE_rr (LDriw_indexed IntRegs:$src1,
> s11_2ExtPred:$offset1),
> (LDriw
ADDRriS11_2:$src2)))>;
> ******************************
I had to modify the above pattern where in the LDriw (the second load in the
COMBINE_rr) is changed to LDriw_indexed s...
2012 May 14
0
[LLVMdev] Register coalescing (Subregs and SuperRegs)
...= COPY %R0<kill>; IntRegs:%vreg0
> 32B %vreg1<def> = LDriw %vreg0, 0; mem:LD4[%a]
> IntRegs:%vreg1,%vreg0
> 48B %vreg2<def> = LDriw_indexed %vreg0<kill>, 4;
> mem:LD4[%add.ptr] IntRegs:%vreg2,%vreg0
> 64B %vreg7<def> = COMBINE_rr %vreg2<kill>, %vreg1<kill>;
> DoubleRegs:%vreg7 IntRegs:%vreg2,%vreg1
> 80B %D0<def> = COPY %vreg7<kill>; DoubleRegs:%vreg7
> ------------------------------------------------------------------
> LDriw and LDriw_indexed load 32 -bit words. So %v...
2012 Jul 09
0
[LLVMdev] Possible issue with EXPANDING POST-RA PSEUDO INSTRS
On Jul 8, 2012, at 3:42 PM, Sergei Larin <slarin at codeaurora.org> wrote:
> ********** EXPANDING POST-RA PSEUDO INSTRS **********
> ********** Function: main
> real copy: %R15<def> = COPY %R4, %D2<imp-use,kill>, %D7<imp-use,kill>,
> %D7<imp-def>
> replaced by: %R15<def> = TFR %R4, %D7<imp-def>
>
> The R4 is a subreg of D2 double
2012 Jul 08
2
[LLVMdev] Possible issue with EXPANDING POST-RA PSEUDO INSTRS
Hello everyone,
I am running into an obscure issue with ExpandPostRA. Does anyone
recognizes the following:
The pass replaces a real copy with a "transfer" instruction:
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: main
real copy: %R15<def> = COPY %R4, %D2<imp-use,kill>, %D7<imp-use,kill>,
%D7<imp-def>
replaced by: