Displaying 18 results from an estimated 18 matches for "doublereg".
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doubleregs
2012 May 14
0
[LLVMdev] Register coalescing (Subregs and SuperRegs)
...tRegs:%vreg0
32B %vreg1<def> = LDriw %vreg0, 0;
mem:LD4[%a],IntRegs:%vreg1,%vreg0
48B %vreg2<def> = LDriw_indexed %vreg0<kill>, 4;
mem:LD4[%add.ptr] IntRegs:%vreg2,%vreg0
64B %vreg7<def> = COMBINE_rr %vreg2<kill>, %vreg1<kill>;
DoubleRegs:%vreg7 IntRegs:%vreg2,%vreg1
80B %D0<def> = COPY %vreg7<kill>; DoubleRegs:%vreg7
------------------------------------------------------------------
LDriw and LDriw_indexed load 32 -bit words. So %vreg1 and %vreg2 are both
32-bit virtual registers. Hexagon has registe...
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td
>> index b563ac3..e50d935 100644
>> --- a/lib/Target/Hexagon/HexagonInstrInfo.td
>> +++ b/lib/Target/Hexagon/HexagonInstrInfo.td
>> @@ -875,19 +875,19 @@ def LDrid_indexed : LDInst<(outs DoubleRegs:$dst),
>> s11_3ImmPred:$offset)))]>;
>>
>> let mayLoad = 1, neverHasSideEffects = 1 in
>> -def LDrid_GP : LDInst<(outs DoubleRegs:$dst),
>> +def LDrid_GP : LDInst2<(outs DoubleRegs:$dst),
>>...
2013 Jan 14
2
[LLVMdev] Splitting live ranges of half-defined registers
...56, 680; IntRegs:%vreg62,%vreg56
%R1<def> = TFRI 1431655766
ADJCALLSTACKDOWN 0, %R29<imp-def>, %R30<imp-def>,
%R31<imp-use>, %R30<imp-use>, %R29<imp-use>
%vreg304:subreg_loreg<def,read-undef> = ADDri_SUBr_V4 %vreg62,
5, %vreg61; DoubleRegs:%vreg304 IntRegs:%vreg62,%vreg61
%vreg519<def> = TFRI 3148; IntRegs:%vreg519
%vreg523<def> = TFRI64 15; DoubleRegs:%vreg523
%R0<def> = COPY %vreg304:subreg_loreg; DoubleRegs:%vreg304
CALLv3 <ga:@foo>, %D0<imp-def,dead>, %D1<imp-d...
2012 Aug 28
5
[LLVMdev] Assert in LiveInterval update
...s:%vreg31
24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;
IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
96B %vreg37<def> = LDriw <fi#-8>,...
2012 May 14
0
[LLVMdev] Register coalescing (Subregs and SuperRegs)
...%vreg1<def> = LDriw %vreg0, 0; mem:LD4[%a]
> IntRegs:%vreg1,%vreg0
> 48B %vreg2<def> = LDriw_indexed %vreg0<kill>, 4;
> mem:LD4[%add.ptr] IntRegs:%vreg2,%vreg0
> 64B %vreg7<def> = COMBINE_rr %vreg2<kill>, %vreg1<kill>;
> DoubleRegs:%vreg7 IntRegs:%vreg2,%vreg1
> 80B %D0<def> = COPY %vreg7<kill>; DoubleRegs:%vreg7
> ------------------------------------------------------------------
> LDriw and LDriw_indexed load 32 -bit words. So %vreg1 and %vreg2 are both
> 32-bit virtual registers....
2012 Aug 30
0
[LLVMdev] Assert in LiveInterval update
...OPY %R0<kill>; IntRegs:%vreg26
> 28B %vreg106<def> = TFRI 16777216;
> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
> 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
> 96B %vre...
2012 Aug 31
2
[LLVMdev] Assert in LiveInterval update
...<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;
IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
96B %vreg37<def>...
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
On Aug 30, 2012, at 1:20 PM, Arnold Schwaighofer <arnolds at codeaurora.org> wrote:
> The code in collectRanges() does:
>
> // Collect ranges for register units. These live ranges are computed on
> // demand, so just skip any that haven't been computed yet.
> if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
> for (MCRegUnitIterator Units(Reg,
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...%vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
> 28B %vreg106<def> = TFRI 16777216;
> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
> 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
> 96B %vreg37<def> = LDriw...
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
The code in collectRanges() does:
// Collect ranges for register units. These live ranges are computed on
// demand, so just skip any that haven't been computed yet.
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
2012 Aug 31
0
[LLVMdev] Assert in LiveInterval update
...<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;
IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
96B %vreg37<def>...
2012 Jul 09
0
[LLVMdev] Possible issue with EXPANDING POST-RA PSEUDO INSTRS
On Jul 8, 2012, at 3:42 PM, Sergei Larin <slarin at codeaurora.org> wrote:
> ********** EXPANDING POST-RA PSEUDO INSTRS **********
> ********** Function: main
> real copy: %R15<def> = COPY %R4, %D2<imp-use,kill>, %D7<imp-use,kill>,
> %D7<imp-def>
> replaced by: %R15<def> = TFR %R4, %D7<imp-def>
>
> The R4 is a subreg of D2 double
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...lt;kill>; IntRegs:%vreg26
>> 28B %vreg106<def> = TFRI 16777216;
>> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
>> 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
>> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
>> 96B...
2012 Aug 28
0
[LLVMdev] Assert in LiveInterval update
On Aug 28, 2012, at 8:18 AM, Sergei Larin <slarin at codeaurora.org> wrote:
>
> I've described that issue (see below) when you were out of town... I think
> I am getting more context on it. Please take a look...
>
> So, in short, when the new MI scheduler performs move of an instruction, it
> does something like this:
>
> // Move the instruction to its new
2012 Jul 08
2
[LLVMdev] Possible issue with EXPANDING POST-RA PSEUDO INSTRS
Hello everyone,
I am running into an obscure issue with ExpandPostRA. Does anyone
recognizes the following:
The pass replaces a real copy with a "transfer" instruction:
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: main
real copy: %R15<def> = COPY %R4, %D2<imp-use,kill>, %D7<imp-use,kill>,
%D7<imp-def>
replaced by:
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...tRegs:%vreg26
> >> 28B %vreg106<def> = TFRI 16777216;
> >> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
> >> 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
> >> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
> >> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
> >...
2012 Sep 03
2
[LLVMdev] Assert in LiveInterval update
...OPY %R0<kill>; IntRegs:%vreg26
> 28B %vreg106<def> = TFRI 16777216;
> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
> 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
> 96B %vre...
2012 Aug 28
2
[LLVMdev] Assert in LiveInterval update
Andy,
I've described that issue (see below) when you were out of town... I think
I am getting more context on it. Please take a look...
So, in short, when the new MI scheduler performs move of an instruction, it
does something like this:
// Move the instruction to its new location in the instruction stream.
MachineInstr *MI = SU->getInstr();
if (IsTopNode) {