Displaying 20 results from an estimated 28 matches for "ldriw".
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...for.cond
> Predecessors according to CFG: BB#0 BB#1
> %vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>; IntRegs:%vreg0,%vreg4,%vreg3
> %vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>; IntRegs:%vreg1,%vreg5,%vreg2
> %vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg2,%vreg0
> %vreg3<def> = ADD_ri %vreg2, 8; IntRegs:%vreg3,%vreg2
> %vreg6<def> = CMPEQri %vreg2, 0; PredRegs:%vreg6 IntRegs:%vreg2
> JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vre...
2012 Apr 26
2
[LLVMdev] MemRefs in a Load Instruction
...********************
def: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1,
s11_2ExtPred:$offset1)))),
(i32 32))),
(i64 (zextloadi32 ADDRriS11_2:$src2)))),
(i64 (COMBINE_rr (LDriw_indexed IntRegs:$src1,
s11_2ExtPred:$offset1),
(LDriw ADDRriS11_2:$src2)))>;
******************************
Without getting into too much detail, all that the pattern is doing is
combining the results of two 32 bit loads into a 64 bit value.
The t...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...%vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>;
IntRegs:%vreg0,%vreg4,%vreg3
%vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>;
IntRegs:%vreg1,%vreg5,%vreg2 <<<<<<<<<<< Use of that dummy value.
%vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg2,%vreg0
By the time it has gotten to the scheduler, it became this:
BB#0: derived from LLVM BB %entry
%vreg9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
Successors according to CFG: BB#1
BB#1: derived f...
2012 Jun 14
1
[LLVMdev] Assert in live update from MI scheduler.
Sergei,
Absolutely right, the copy/ldriw should not be reordered. I was attempting to explain that I consider it a phi-elimination bug, not a DAG builder bug. Liveness will also have problems with this code in the long run.
To avoid confusion, I filed PR13112: Phi elimination generates uninitialized vreg uses, and disabled the SSA check...
2012 Aug 28
5
[LLVMdev] Assert in LiveInterval update
...R3 = [0B,48r:0)[368r,416r:5)...
R4 = [0B,32r:0)[384r,416r:4)...
R5 = [0B,32r:0)[400r,416r:4)...
I schedule the following instruction (48B):
0B BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %D1 %D2
8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
12B %vreg30<def> = LDriw <fi#-1>, 0;
mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
IntRegs:%vreg31
24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;
IntRegs:%vreg106<<<<<<...
2012 Aug 30
0
[LLVMdev] Assert in LiveInterval update
...= [0B,32r:0)[400r,416r:4)...
>
> I schedule the following instruction (48B):
>
> 0B BB#0: derived from LLVM BB %entry
> Live Ins: %R0 %R1 %D1 %D2
> 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
> 12B %vreg30<def> = LDriw <fi#-1>, 0;
> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
> IntRegs:%vreg31
> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
> 28B %vreg106<def>...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...d from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
%vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>;
IntRegs:%vreg0,%vreg4,%vreg3
%vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>;
IntRegs:%vreg1,%vreg5,%vreg2
%vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg2,%vreg0
%vreg3<def> = ADD_ri %vreg2, 8; IntRegs:%vreg3,%vreg2
%vreg6<def> = CMPEQri %vreg2, 0; PredRegs:%vreg6 IntRegs:%vreg2
JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
JMP...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...== MRI.def_end())
>
> should guarantee? From it there must be more than one definition in MRI.def
> for that reg for it to work...
>
>
>
>
> To connect it to the original example... When parsing (BU order) this
> instruction:
>
> SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
>
> The %vreg10<def> never inserted to VRegDefs, so with next instruction:
>
> SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
>
> Anti dep on %vreg10 is never created.
Thanks for the detailed exp...
2012 Aug 31
2
[LLVMdev] Assert in LiveInterval update
...= [0B,32r:0)[384r,416r:4)...
R5 = [0B,32r:0)[400r,416r:4)...
I schedule the following instruction (48B):
0B BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %D1 %D2
8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
12B %vreg30<def> = LDriw <fi#-1>, 0;
mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
IntRegs:%vreg31
24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;
IntRegs...
2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
...g9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
Successors according to CFG: BB#1
48B BB#1: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
96B %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg10,%vreg9
112B %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
128B %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10
176B JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%v...
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
On Aug 30, 2012, at 1:20 PM, Arnold Schwaighofer <arnolds at codeaurora.org> wrote:
> The code in collectRanges() does:
>
> // Collect ranges for register units. These live ranges are computed on
> // demand, so just skip any that haven't been computed yet.
> if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
> for (MCRegUnitIterator Units(Reg,
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...B,32r:0)[384r,416r:4)...
> R5 = [0B,32r:0)[400r,416r:4)...
>
> I schedule the following instruction (48B):
>
> 0B BB#0: derived from LLVM BB %entry
> Live Ins: %R0 %R1 %D1 %D2
> 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
> 12B %vreg30<def> = LDriw <fi#-1>, 0;
> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
> IntRegs:%vreg31
> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
> 28B %vreg106<def> = TFRI 16777216;
> IntRegs:%v...
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
The code in collectRanges() does:
// Collect ranges for register units. These live ranges are computed on
// demand, so just skip any that haven't been computed yet.
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
2012 Aug 31
0
[LLVMdev] Assert in LiveInterval update
...= [0B,32r:0)[384r,416r:4)...
R5 = [0B,32r:0)[400r,416r:4)...
I schedule the following instruction (48B):
0B BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %D1 %D2
8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
12B %vreg30<def> = LDriw <fi#-1>, 0;
mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
IntRegs:%vreg31
24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;
IntRegs...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...ga:@xx_stack>; IntRegs:%vreg9
> Successors according to CFG: BB#1
>
> 48B BB#1: derived from LLVM BB %for.cond
> Predecessors according to CFG: BB#0 BB#1
> 80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
> 96B %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
> IntRegs:%vreg10,%vreg9
> 112B %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
> 128B %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10
> 176B JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-...
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...6r:4)...
>>
>> I schedule the following instruction (48B):
>>
>> 0B BB#0: derived from LLVM BB %entry
>> Live Ins: %R0 %R1 %D1 %D2
>> 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
>> 12B %vreg30<def> = LDriw <fi#-1>, 0;
>> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
>> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
>> IntRegs:%vreg31
>> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
>> 28B %vreg...
2012 Apr 27
0
[LLVMdev] MemRefs in a Load Instruction
...f: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1,
>
> s11_2ExtPred:$offset1)))),
> (i32 32))),
> (i64 (zextloadi32
ADDRriS11_2:$src2)))),
> (i64 (COMBINE_rr (LDriw_indexed IntRegs:$src1,
> s11_2ExtPred:$offset1),
> (LDriw
ADDRriS11_2:$src2)))>;
> ******************************
I had to modify the above pattern where in the LDriw (the second load in the
COMBINE_rr) is changed to LDriw_indexed similar...
2012 Aug 28
0
[LLVMdev] Assert in LiveInterval update
On Aug 28, 2012, at 8:18 AM, Sergei Larin <slarin at codeaurora.org> wrote:
>
> I've described that issue (see below) when you were out of town... I think
> I am getting more context on it. Please take a look...
>
> So, in short, when the new MI scheduler performs move of an instruction, it
> does something like this:
>
> // Move the instruction to its new
2012 Jun 13
4
[LLVMdev] Assert in live update from MI scheduler.
...o the MI DAG dep
constructor. See this:
SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
# preds left : 0
# succs left : 0
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg10,%vreg9
# preds left : 0
# succs left : 3
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
Successors:
val SU(3): Latency=1
val SU(2): Latency=1
antiSU(2): Latenc...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...is this statement
if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
should guarantee? From it there must be more than one definition in MRI.def
for that reg for it to work...
To connect it to the original example... When parsing (BU order) this
instruction:
SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
The %vreg10<def> never inserted to VRegDefs, so with next instruction:
SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
Anti dep on %vreg10 is never created.
Thanks.
Sergei
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