search for: subreg

Hi, Recently on trunk, the ovlaps list for a register got a dual entry on my target, which caused the RA to crash. Reg Subreg1 Subreg b Subreg2 Subreg b I have a register with two subregs that have subreg b in common. This causes the SuperReg to appear twice in the ovelaps list for Subreg b. As this causes a register allocator to crasch (it evicts a register, and then inremenets the *AliasI, but the data struc...

There's an assert at line 192, lib/CodeGen/RegisterScavenging.cpp that appears to get tripped on targets that don't have subregisters defined: bool SubUsed = false; for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) if (isUsed(SubReg)) { SubUsed = true; break; } assert(SubUsed && "U...

...by the backend tools. It does not hurt anything but should not be there. // We have banks of 32 registers each. class MipsReg<string n> : Register<n> { field bits<5> Num; let Namespace = "Mips"; } class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> { field bits<4> Num; let Namespace = "ARM"; let SubRegs = subregs; // All bits of ARM registers with sub-registers are covered by sub-registers. let CoveredBySubRegs = 1; } class ARMFReg<bits<6> num, string n> : Register&lt...

...r cannot trivially coalesce a copy, say C,, it calls AdjustCopiesBackFrom. In this function, we try to see if have this situation. A3 = B0 ..... ..... B1 = A3 <--The copy C And if so, we check if we can merge the two ranges of B into a single range. However, this is not safe if A3 is a subreg define while A3 is not a subreg use. For instance, consider this code (part of a single block loop). MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30, 2, // Post Inc. Load. Vreg7 is a 64bit reg. MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg...

Hi Jakob, Thanks for your reply. > > The <undef> flag goes on NewMI_1 because the virtual register B isn't live > before that instruction. > > But you probably shouldn't be doing this yourself. Your NewMI code isn't in > SSA form because B has multiple definitions. Just use a REG_SEQUENCE > instruction, and let the register allocator do the transformation

I'm running into a problem with subregs during trivial coalescing in the linear scan allocator. Should RALinScan::attemptTrivialCoalescing be allowed to coalesce a COPY that uses a subreg as a destination? I've got the following sequence of code (unfortunately for an out of tree target) that is moving 32 and 64 bit sub-registers a...

What's the best way to get an SDNode through to DAG scheduling without getting mangled during Lowering/ISel? When should subregs be flattened to actual registers: AsmPrinter? Somewhere in LiveIntervals, during RegAlloc? Is there are common API used to turn vregs into physregs that could be changed to flatten any subregs in a central location? -- Christopher Lamb

Thanks for the detailed response. On Apr 23, 2007, at 4:22 PM, Chris Lattner wrote: > Right. Evan is currently focusing on getting the late stages of > the code > generator (e.g. livevars) to be able to understand arbitrary machine > instrs in the face of physreg subregs. This lays the groundwork for > handling vreg subregs, but won't solve it directly. Is the work Evan doing a prerequisite for supporting vreg subregs? Is there a PR for the feature Evan is working on? >> Is any of this kind of work planned? The addition of those >> MRegisterI...

Hi, I'm facing a problem in my BE while trying to remove certain copies. Here is a code snippet which I would like to optimize %vreg1<def> = READF32r; vRRegs:%vreg1 %vreg2<def> = COPY %vreg1:rsub_h; iRSubRegs:%vreg2 vRRegs:%vreg1 %vreg3<def> = COPY %vreg1:rsub_l; iRSubRegs:%vreg3 vRRegs:%vreg1 This code produces subreg-to-subreg copies but I would like to have direct uses of vreg1's subregisters instead. I tried to add RAhints in order to form identity copies (vreg1 and vreg2/3 should be a...

Ugh. Management lobotomy kicked in. Need to RTFC better. On Thu, Feb 25, 2010 at 6:18 PM, Scott Michel <scooter.phd at gmail.com> wrote: > There's an assert at line 192, lib/CodeGen/RegisterScavenging.cpp that > appears to get tripped on targets that don't have subregisters defined: > > bool SubUsed = false; > for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); > unsigned SubReg = *SubRegs; ++SubRegs) > if (isUsed(SubReg)) { > SubUsed = true; > break; > } &g...

On May 11, 2012, at 6:35 AM, Jonas Paulsson <jonas.paulsson at ericsson.com> wrote: > Hi, > > Recently on trunk, the ovlaps list for a register got a dual entry on my target, which caused the RA to crash. > > Reg > Subreg1 > Subreg b > Subreg2 > Subreg b > > I have a register with two subregs that have subreg b in common. This causes the SuperReg to appear twice in the ovelaps list for Subreg b This should be fixed in r156629. /jakob -------------- next part -------------- An HTML attac...

The new SUBREG target-independent instructions aren't getting mayLoad/mayStore flags set correctly. For example, in the generated X86GenInstrInfo.inc file, there is only one entry for INSERT_SUBREG: { 5, 4, 1, 0, "INSERT_SUBREG", 0, 0, NULL, NULL, OperandInfo107 }, // Inst #5...

...gt; calls AdjustCopiesBackFrom. In this function, we try to see if have this > situation. > > A3 = B0 > ..... > ..... > B1 = A3 <--The copy C > > And if so, we check if we can merge the two ranges of B into a single range. > However, this is not safe if A3 is a subreg define while A3 is not a subreg > use. > For instance, consider this code (part of a single block loop). > > MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30, > 2, // Post Inc. Load. Vreg7 is a 64bit reg. > MI2:: %vreg7:subreg_hireg<def&g...

...mean by "mangled"? Please clarify. My mangled I mean the nodes shouldn't be isel'ed into anything else because they need to survive through to scheduling. Is there a preferred means of having those nodes skipped during selection and lowering? >> >> When should subregs be flattened to actual registers: AsmPrinter? >> Somewhere in LiveIntervals, during RegAlloc? > > You mean turning part of a larger physical register into a sub- > register? Yes. > I would think LiveIntervals or else copy coalescing might > not work right. Ok. Can you give...

...ing but should not be there. > > // We have banks of 32 registers each. > class MipsReg<string n> : Register<n> { > field bits<5> Num; > let Namespace = "Mips"; > } > > class ARMReg<bits<4> num, string n, list<Register> subregs = []> : > Register<n> { > field bits<4> Num; > let Namespace = "ARM"; > let SubRegs = subregs; > // All bits of ARM registers with sub-registers are covered by > sub-registers. > let CoveredBySubRegs = 1; > } > > class A...

...ieces, so we can tackle these > one at > a time. <snip> > 4. The DAG scheduler pass (which creates machine instrs from dag > nodes) > currently thinks of register operands as simple unsigned's for > vreg > #'s. This needs to be extended to be vreg+subreg pairs (see > 'CreateVirtualRegisters'). > 5. We need to decide how to represent subregs in the DAG. Your > SDSubOperand idea is fine, but I don't think it needs to be an > actual > new subclass of SDOperand. Instead, it could just be a binary > SDNode...

...Gohman wrote: >>> #2 is conceptually correct. The problem is 128 bit XMM0 is the same >>> register as 32 bit (or 64 bit) XMM0. So it's not possible to define >>> the super-register / sub-register relationship. >> >> I don't understand the problem with subregs here. Is it just a >> naming issue? That can be solved by introducing alternate names, >> like XMM0_32 and XMM0_64, for each of the subregs. They could >> still be printed as "xmm0" in the assembly output of course. > > this is what the PPC64 backend does. "...

...ard <ivanllopard at gmail.com> wrote: > Hi, > > I'm facing a problem in my BE while trying to remove certain copies. > Here is a code snippet which I would like to optimize > > %vreg1<def> = READF32r; vRRegs:%vreg1 > %vreg2<def> = COPY %vreg1:rsub_h; iRSubRegs:%vreg2 vRRegs:%vreg1 > %vreg3<def> = COPY %vreg1:rsub_l; iRSubRegs:%vreg3 vRRegs:%vreg1 > > This code produces subreg-to-subreg copies but I would like to have > direct uses of vreg1's subregisters instead. > I tried to add RAhints in order to form identity copies (vreg1...

On Jun 11, 2007, at 6:14 PM, Christopher Lamb wrote: > > What's the best way to get an SDNode through to DAG scheduling > without getting mangled during Lowering/ISel? What do you mean by "mangled"? Please clarify. > > When should subregs be flattened to actual registers: AsmPrinter? > Somewhere in LiveIntervals, during RegAlloc? You mean turning part of a larger physical register into a sub- register? I would think LiveIntervals or else copy coalescing might not work right. Evan > > Is there are common API used to t...

...t be isel'ed into anything else because > they need to survive through to scheduling. Is there a preferred means of > having those nodes skipped during selection and lowering? You'll have to teach legalize and isel about these nodes, just like they know about ISD::Register nodes. subregs will be a new first-class node type that all of the dag stuff will have to know about (at least to pass them through). >> > When should subregs be flattened to actual registers: AsmPrinter? >> > Somewhere in LiveIntervals, during RegAlloc? This should definitely be done dur...