Displaying 20 results from an estimated 150 matches for "vreg2".
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2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...Successors according to CFG: BB#1
>
> BB#1: derived from LLVM BB %for.cond
> Predecessors according to CFG: BB#0 BB#1
> %vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>; IntRegs:%vreg0,%vreg4,%vreg3
> %vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>; IntRegs:%vreg1,%vreg5,%vreg2
> %vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg2,%vreg0
> %vreg3<def> = ADD_ri %vreg2, 8; IntRegs:%vreg3,%vreg2
> %vreg6<def> = CMPEQri %vreg2, 0; PredRegs:%vreg6 IntRegs:%vreg2
>...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...ut(float %23, i32 6)
%24 = extractelement <4 x float> %9, i32 3
call void @llvm.AMDGPU.store.output(float %24, i32 7)
ret void
}
# *** IR Dump Before Expand ISel Pseudo-instructions ***:
# Machine code for function main: SSA
Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3
Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
BB#0: derived from LLVM BB %0
Live Ins: %T1_W %T1_Z %T1_Y %T1_X
%vreg3<def> = COPY %T1_X; R600_TReg32:%vreg3
%vreg2<def> = COPY %T1_Y; R600_TReg32:%vreg2
%vreg1<def> = COPY %T1_Z; R600_TReg32...
2013 Aug 02
0
[LLVMdev] Missing optimization - constant parameter
...gt;[TF=5], %noreg; mem:LD8[GOT] GR64:%vreg0
32B %vreg1<def> = MOV64rm %RIP, 1, %noreg, <ga:@p>[TF=5],
%noreg; mem:LD8[GOT] GR64:%vreg1
48B MOV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0;
mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0
64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2
80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2;
mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2
96B %RDI<def> = COPY %vreg2; GR64:%vreg2
112B TCRETURNdi64 <ga:@xtr>, 0, <regmask>, %RSP...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...gt;; IntRegs:%vreg4
Successors according to CFG: BB#1
BB#1: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
%vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>;
IntRegs:%vreg0,%vreg4,%vreg3
%vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>;
IntRegs:%vreg1,%vreg5,%vreg2
%vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg2,%vreg0
%vreg3<def> = ADD_ri %vreg2, 8; IntRegs:%vreg3,%vreg2
%vreg6<def> = CMPEQri %vreg2, 0; PredRegs:%vreg6 IntRegs:%vreg2
JMP_cNot %vre...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...gt;; IntRegs:%vreg4
Successors according to CFG: BB#1
BB#1: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
%vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>;
IntRegs:%vreg0,%vreg4,%vreg3
%vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>;
IntRegs:%vreg1,%vreg5,%vreg2 <<<<<<<<<<< Use of that dummy value.
%vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg2,%vreg0
By the time it has gotten to the scheduler, it became this:
BB#0: derived fro...
2013 Aug 02
2
[LLVMdev] Missing optimization - constant parameter
For the little C test program where a constant is stored in memory and
also
used as a parameter:
#include <stdint.h>
uint64_t val, *p;
extern uint64_t xtr( uint64_t);
uint64_t caller() {
uint64_t x;
p = &val;
x = 12345123400L;
*p = x;
return xtr(x);
}
clang (3.2, 3.3 and svn) generates the following X86 code (at -O3):
caller:
movq
2012 Jun 14
1
[LLVMdev] Assert in live update from MI scheduler.
...Successors according to CFG: BB#1
>
> BB#1: derived from LLVM BB %for.cond
> Predecessors according to CFG: BB#0 BB#1
> %vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>; IntRegs:%vreg0,%vreg4,%vreg3
> %vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>; IntRegs:%vreg1,%vreg5,%vreg2 <<<<<<<<<<< Use of that dummy value.
> %vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg2,%vreg0
>
>
> By the time it has gotten to the scheduler, it became this:
>...
2013 Aug 02
2
[LLVMdev] Missing optimization - constant parameter
...8[GOT] GR64:%vreg0
> 32B %vreg1<def> = MOV64rm %RIP, 1, %noreg, <ga:@p>[TF=5],
> %noreg; mem:LD8[GOT] GR64:%vreg1
> 48B MOV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0;
> mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0
> 64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2
> 80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2;
> mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2
> 96B %RDI<def> = COPY %vreg2; GR64:%vreg2
> 112B TCRETURNdi64 <ga:@xtr>, 0, &...
2017 Aug 17
2
reg coalescing improvements
...%R2D<def> = LGR %R4D<kill> // R2 = R4
could be optimized to ->
%R2D<def> = LA %R2D<kill>, 4, %noreg // R2 = R2 + 4
The reason this wasn't coalesced, is because of overlapping during
coalescing:
864B %vreg11<def> = LA %vreg2, 4, %noreg
880B %vreg16<def> = LLCMux %vreg2, 4, %noreg
928B %vreg2<def> = COPY %vreg11
It seems that if this had been rescheduled to
880B %vreg16<def> = LLCMux %vreg2, 4, %noreg
864B %vreg11<def> = LA %vreg2, 4, %noreg
928B...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...his early exit is taken:
>
> // SSA defs do not have output/anti dependencies.
> // The current operand is a def, so we have at least one.
> if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
> return;
>
> we do not ever get to this point:
>
> VRegDefs.insert(VReg2SUnit(Reg, SU));
>
> But later, when checking for anti dependency for another MI here:
>
> void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
> ...
> // Add antidependence to the following def of the vreg it uses.
> VReg2SUnitMap::iterator DefI = VRegDefs....
2012 May 14
0
[LLVMdev] Register coalescing (Subregs and SuperRegs)
Hi,
Consider this MI code from the hexagon backend.
------------------------------------------------------------------
16B %vreg0<def> = COPY %R0<kill>; IntRegs:%vreg0
32B %vreg1<def> = LDriw %vreg0, 0;
mem:LD4[%a],IntRegs:%vreg1,%vreg0
48B %vreg2<def> = LDriw_indexed %vreg0<kill>, 4;
mem:LD4[%add.ptr] IntRegs:%vreg2,%vreg0
64B %vreg7<def> = COMBINE_rr %vreg2<kill>, %vreg1<kill>;
DoubleRegs:%vreg7 IntRegs:%vreg2,%vreg1
80B %D0<def> = COPY %vreg7<kill>; DoubleRegs:%vreg7...
2012 Jan 24
1
[LLVMdev] Req-sequence, partial defs
Hi,
I'm having an issue with subregisters on my target.
With a pseudo that writes to a 32 bit reg:
%vreg20<def> = toHi16_low0_pseudo %vreg2; reg32:%vreg20 hi16:%vreg2
expands to
%vreg2<def> = COPY %a2h; hi16:%vreg2
%vreg43<def> = mov 0, pred:0, pred:%noreg, %ac0<imp-use>, %ac1<imp-use>; lo16:%vreg43
%vreg20<def> = REG_SEQUENCE %vreg2, hi16,...
2012 Mar 08
1
[LLVMdev] Register coalescing
...he
LowerFormalArgument() routine, but then the register allocator and
coalescer are resisting coalescing the COPY MI's for various reasons - for
example, the read-only register class contains too few registers and the
live range threshold cancels the coalescing.
A simple example (post-ISEL):
%vreg2<def> = COPY %C1; GPReg:%vreg2
...
%vreg11<def> = MUL %vreg7, %vreg2; GPreg:%vreg11,%vreg7,%vreg2
I'd want it to propagate %C1 into the MUL, replacing %vreg2. How is this
supposed to work? Is there a DAG operation or MF pass that should handle
this before regalloc, or some other mea...
2012 May 14
0
[LLVMdev] Register coalescing (Subregs and SuperRegs)
...code from the hexagon backend.
> ------------------------------------------------------------------
> 16B %vreg0<def> = COPY %R0<kill>; IntRegs:%vreg0
> 32B %vreg1<def> = LDriw %vreg0, 0; mem:LD4[%a]
> IntRegs:%vreg1,%vreg0
> 48B %vreg2<def> = LDriw_indexed %vreg0<kill>, 4;
> mem:LD4[%add.ptr] IntRegs:%vreg2,%vreg0
> 64B %vreg7<def> = COMBINE_rr %vreg2<kill>, %vreg1<kill>;
> DoubleRegs:%vreg7 IntRegs:%vreg2,%vreg1
> 80B %D0<def> = COPY %vreg7<kill>; Dou...
2013 May 13
1
[LLVMdev] Tracking down a SELECT expansion to predicated moves
...p Before Expand ISel Pseudo-instructions ***:
# Machine code for function main: SSA
Function Live Outs: %r8
BB#0: derived from LLVM BB %entry
%vreg0<def> = MOVL_GA <ga:@b>; GR:%vreg0
%vreg1<def> = LDSHri %vreg0<kill>, 0; mem:LD4[@b] GR:%vreg1,%vreg0
%vreg2<def> = MOVIMM21 0; GR:%vreg2
%vreg3<def> = CMPGT %vreg1<kill>, %vreg2; PR:%vreg3 GR:%vreg1,%vreg2
%vreg4<def> = MOVIMM21 8; GR:%vreg4
%vreg5<def> = MOV %vreg4<kill>; GR:%vreg5,%vreg4
%vreg6<def> = MOVIMM21 23; GR:%vreg6...
2012 Jul 05
3
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
...lf. Your NewMI code isn't
in
> SSA form because B has multiple definitions. Just use a REG_SEQUENCE
> instruction, and let the register allocator do the transformation for you.
Aaargh. So you mean something like this ?
New_MI_1:: Vreg1 = 0 ; Vreg1 and Vreg2
are 32 bit virt. regs.
New_MI_2:: Vreg2 = COPY C:lo_sub_reg.
New_MI_3:: B= REG_SEQUENCE<Vreg1, hi_sub_reg, Vreg2, lo_sub_reg> ; B is a
64 bit virt reg.
TIA,
Pranav
2012 Nov 10
0
[LLVMdev] register scavenger
Hi Reed,
the register scavenger (RS) also keeps track of live registers. This
way it "knows" that the register that was spilled/restored far apart
is available.
Let say you had the following code. You need to find a register to
keep vreg1 and vreg2 in.
R1 = .... // <- RS current liveness state; we have called
RS->forward(It) where It points to here
vreg1 = add SP, 1000
... = load vreg1
... // more code
vreg2 = add SP, 2000
... = load vreg
... = R1
When you come to the definition of vreg1 you (or lets say the
scavengeFrameVirtualRegs...
2013 Aug 05
0
[LLVMdev] Missing optimization - constant parameter
...gt; 32B %vreg1<def> = MOV64rm %RIP, 1, %noreg, <ga:@p>[TF=5],
> > %noreg; mem:LD8[GOT] GR64:%vreg1
> > 48B MOV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0;
> > mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0
> > 64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2
> > 80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2;
> > mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2
> > 96B %RDI<def> = COPY %vreg2; GR64:%vreg2
> > 112B TCRETURNdi64 &...
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...Dump After MachineFunction Printer ***:
# Machine code for function addproddivConst: Post SSA
Function Live Ins: %FA_ROFF1 in %vreg0
0B BB#0: derived from LLVM BB %entry
Live Ins: %FA_ROFF1
16B %vreg0<def> = COPY %FA_ROFF1; FPUaOffsetClass:%vreg0
32B %vreg2<def> = MOVSUTO_A_iSLo 1077936128; FPUaOffsetClass:%vreg2
48B %vreg3<def> = FMUL_A_oo %vreg0, %vreg2, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg3 FPUaOffsetClass:%vreg0,%vreg2
64B %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMUL...
2012 Mar 28
2
[LLVMdev] Remove subreg copies
Hi,
I'm facing a problem in my BE while trying to remove certain copies.
Here is a code snippet which I would like to optimize
%vreg1<def> = READF32r; vRRegs:%vreg1
%vreg2<def> = COPY %vreg1:rsub_h; iRSubRegs:%vreg2 vRRegs:%vreg1
%vreg3<def> = COPY %vreg1:rsub_l; iRSubRegs:%vreg3 vRRegs:%vreg1
This code produces subreg-to-subreg copies but I would like to have
direct uses of vreg1's subregisters instead.
I tried to add RAhints in order to form ident...