search for: vreg7

...0; PredRegs:%vreg6 IntRegs:%vreg2 > JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6 > JMP <BB#2> > Successors according to CFG: BB#2 BB#1 > > BB#2: derived from LLVM BB %for.end > Predecessors according to CFG: BB#1 > %vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any pointer") IntRegs:%vreg7,%vreg1 > STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>; mem:ST4[@yy_instr](tbaa=!"any pointer") IntRegs:%vreg7 > %vreg8<def> = IMPLICIT_DEF; IntRegs:%vreg8 &...

Hi, I'm having some trouble wirting an instruction in the X86 backend. I made a new intrinsic and I wrote a custom inserter for my intrinsic in the X86 backend. Everything works fine, except for one instruction that I can't find how to write. I want to add this instruction in one of my machine basic block: mov [rdi], 0 How can I achieve that with the LLVM api? I tried several

...sable-cross-class-join" to be sure the resulting code is ok? I have several cases where cross class joins are carried out that makes the code turn out illegal, because the "new" register class is not allowed in all instructions where it is now used. For example, by joining %vreg4, %vreg7 and %vreg9 the following code %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4 %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7 %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9 is turned into %vreg17<def> = load %...

...;def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10 JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6 JMP <BB#2> Successors according to CFG: BB#2 BB#1 BB#2: derived from LLVM BB %for.end Predecessors according to CFG: BB#1 %vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any pointer") IntRegs:%vreg7,%vreg1 STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>; mem:ST4[@yy_instr](tbaa=!"any pointer") IntRegs:%vreg7 JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-u...

...lass:%vreg4 FPUaROUTMULRegisterClass:%vreg3 80B %vreg5<def> = MOVSUTO_A_iSLo 1056964608; FPUaOffsetClass:%vreg5 96B %vreg6<def> = FMUL_A_oo %vreg0, %vreg5, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg6 FPUaOffsetClass:%vreg0,%vreg5 112B %vreg7<def> = COPY %vreg6; FPUaOffsetClass:%vreg7 FPUaROUTMULRegisterClass:%vreg6 128B %vreg8<def> = FADD_A_oo %vreg4, %vreg7, %RFLAGA<imp-def,dead>; FPUaROUTADDRegisterClass:%vreg8 FPUaOffsetClass:%vreg4,%vreg7 144B %FA_ROFF0<def> = COPY %vreg8; FPUaROUTADDRe...

...0; PredRegs:%vreg6 IntRegs:%vreg10 > JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6 > JMP <BB#2> > Successors according to CFG: BB#2 BB#1 > > BB#2: derived from LLVM BB %for.end > Predecessors according to CFG: BB#1 > %vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any pointer") IntRegs:%vreg7,%vreg1 > STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>; mem:ST4[@yy_instr](tbaa=!"any pointer") IntRegs:%vreg7 > JMPR %PC<imp-def>, %R31<imp-use>, %R0&...

...o be sure the resulting code is ok? No. > I have several cases where cross class joins are carried out that makes > the code turn out illegal, because the "new" register class is not > allowed in all instructions where it is now used. > > For example, by joining %vreg4, %vreg7 and %vreg9 the following code > > %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4 > %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7 > %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9 > > is turned into > &...

...RESERVE_REG 0 %vreg4<def> = FNEG_R600 %vreg3; R600_Reg32:%vreg4 R600_TReg32:%vreg3 %vreg5<def> = MOV_IMM_F32 0.000000e+00; R600_Reg32:%vreg5 %vreg6<def> = ADD 0, 0, 1, 0, 0, 0, %vreg4<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg6,%vreg4,%vreg5 %vreg7<def> = FNEG_R600 %vreg2; R600_Reg32:%vreg7 R600_TReg32:%vreg2 %vreg8<def> = ADD 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg8,%vreg7,%vreg5 %vreg10<def> = IMPLICIT_DEF; R600_Reg128:%vreg10 %vreg9<def,tied1> = INSE...

...ulien <julien.rinaldini at heig-vd.ch> wrote: > > Hum, in fact, I'm still a bit lost ;) > > It seems to works in -O0, but in -O1, -O2 and -O3, I got this error (+ the dump of the function): > > # Machine code for function foo: Post SSA > Function Live Ins: %RDI in %vreg7 > > BB#0: derived from LLVM BB %entry > Live Ins: %RDI > %vreg7<def> = COPY %RDI; GR64:%vreg7 > %vreg1<def> = MOV64rm %vreg7, 1, %noreg, 8, %noreg; mem:LD8[%args.03](tbaa=<badref>) GR64:%vreg1,%vreg7 > TEST64rr %vreg1, %vreg1, %EFLAGS<...

...lt;def> = CMPEQri %vreg2, 0; PredRegs:%vreg6 IntRegs:%vreg2 JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6 JMP <BB#2> Successors according to CFG: BB#2 BB#1 BB#2: derived from LLVM BB %for.end Predecessors according to CFG: BB#1 %vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any pointer") IntRegs:%vreg7,%vreg1 STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>; mem:ST4[@yy_instr](tbaa=!"any pointer") IntRegs:%vreg7 %vreg8<def> = IMPLICIT_DEF; IntRegs:%vreg8 %R0&...

...is situation. A3 = B0 ..... ..... B1 = A3 <--The copy C And if so, we check if we can merge the two ranges of B into a single range. However, this is not safe if A3 is a subreg define while A3 is not a subreg use. For instance, consider this code (part of a single block loop). MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30, 2, // Post Inc. Load. Vreg7 is a 64bit reg. MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg<kill> // This is the A3 = B0 above. MI3:: %vreg31<def> = ADD_rr %vreg31<kill>, %vreg32:subreg_lo...

...--------- 16B %vreg0<def> = COPY %R0<kill>; IntRegs:%vreg0 32B %vreg1<def> = LDriw %vreg0, 0; mem:LD4[%a],IntRegs:%vreg1,%vreg0 48B %vreg2<def> = LDriw_indexed %vreg0<kill>, 4; mem:LD4[%add.ptr] IntRegs:%vreg2,%vreg0 64B %vreg7<def> = COMBINE_rr %vreg2<kill>, %vreg1<kill>; DoubleRegs:%vreg7 IntRegs:%vreg2,%vreg1 80B %D0<def> = COPY %vreg7<kill>; DoubleRegs:%vreg7 ------------------------------------------------------------------ LDriw and LDriw_indexed load 32 -bit words. S...

...bel %loop_bb } The code above is triggering a assertion failure when adjusting the live intervals, since OldFMAReg (%vreg12 in debug info) is actually defined in two blocks. I wonder if we can fix this by making the transformation simpler, that is, instead of doing: %vreg12<def> = COPY %vreg7; VSSRC:%vreg12,%vreg7 %vreg12<def,tied1> = XSMADDASP %vreg12<tied0>, %vreg0, %vreg4; VSSRC:%vreg12,%vreg0 F4RC:%vreg4 -> %vreg0<def,tied1> = XSMADDMSP %vreg0<tied0>, %vreg4, %vreg7; VSSRC:%vreg0,%vreg7 F4RC:%vreg4 , we do: %vreg12<def> = COPY %vreg7; VSS...

On Jun 13, 2012, at 10:49 AM, Sergei Larin <slarin at codeaurora.org> wrote: > So if this early exit is taken: > > // SSA defs do not have output/anti dependencies. > // The current operand is a def, so we have at least one. > if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) > return; > > we do not ever get to this point: > >

...def> = MOVIMM21 0; GR:%vreg2 %vreg3<def> = CMPGT %vreg1<kill>, %vreg2; PR:%vreg3 GR:%vreg1,%vreg2 %vreg4<def> = MOVIMM21 8; GR:%vreg4 %vreg5<def> = MOV %vreg4<kill>; GR:%vreg5,%vreg4 %vreg6<def> = MOVIMM21 23; GR:%vreg6 %vreg7<def,tied1> = CMOV %vreg5<tied0>, %vreg6<kill>, %vreg3<kill>; GR:%vreg7,%vreg5,%vreg6 PR:%vreg3 %vreg8<def> = MOVL_GA <ga:@a>; GR:%vreg8 STHri %vreg8<kill>, 0, %vreg7<kill>; mem:ST4[@a] GR:%vreg8,%vreg7 %r8<def> = COPY %vr...

Hi Jakob, Thanks for your reply. > > The <undef> flag goes on NewMI_1 because the virtual register B isn't live > before that instruction. > > But you probably shouldn't be doing this yourself. Your NewMI code isn't in > SSA form because B has multiple definitions. Just use a REG_SEQUENCE > instruction, and let the register allocator do the transformation

...mize-regalloc -O0. The function is meaningless - with -O3 it just returns zero. It contains two nested loops, with a call inside the inner loop, which is a CFG-diamond. The PHI-nodes look like this in the inner loop: BB#5: // Inner loop header Predecessors according to CFG: BB#1 BB#4 vreg7<def> = PHI %vreg29, <BB#1>, %vreg4, <BB#4> ... Successors according to CFG: BB#2 BB#6 BB#2: Predecessors according to CFG: BB#5 ... Successors according to CFG: BB#3 BB#4 BB#3: Predecessors according to CFG: BB#2 call() %vreg46<def> =...

...%vreg0<def> = COPY %R0<kill>; IntRegs:%vreg0 > 32B %vreg1<def> = LDriw %vreg0, 0; mem:LD4[%a] > IntRegs:%vreg1,%vreg0 > 48B %vreg2<def> = LDriw_indexed %vreg0<kill>, 4; > mem:LD4[%add.ptr] IntRegs:%vreg2,%vreg0 > 64B %vreg7<def> = COMBINE_rr %vreg2<kill>, %vreg1<kill>; > DoubleRegs:%vreg7 IntRegs:%vreg2,%vreg1 > 80B %D0<def> = COPY %vreg7<kill>; DoubleRegs:%vreg7 > ------------------------------------------------------------------ > LDriw and LDriw_indexed lo...

...vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10 176B JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6 192B JMP <BB#2> Successors according to CFG: BB#2 BB#1 208B BB#2: derived from LLVM BB %for.end Predecessors according to CFG: BB#1 224B %vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any pointer") IntRegs:%vreg7,%vreg1 240B STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>; mem:ST4[@yy_instr](tbaa=!"any pointer") IntRegs:%vreg7 256B JMPR %PC<imp-def>, %R31<imp-use>, %R0&lt...

...O3 it just returns zero. >> It contains two nested loops, with a call inside the inner loop, which is a CFG-diamond. >> >> The PHI-nodes look like this in the inner loop: >> >> BB#5: // Inner loop header >> Predecessors according to CFG: BB#1 BB#4 >> vreg7<def> = PHI %vreg29, <BB#1>, %vreg4, <BB#4> >> ... >> Successors according to CFG: BB#2 BB#6 >> >> BB#2: >> Predecessors according to CFG: BB#5 >> ... >> Successors according to CFG: BB#3 BB#4 >> >> BB#3: >> Pred...