llvm dev - Aug 2017

Thursday August 31 2017
TimeRepliesSubject
11:33PM 1 tsan_interface_java.h; any users? reviving https://github.com/google/java-thread-sanitizer?
10:19PM 0 [RFC] Value Range Based Optimization Opportunity in LLVM
10:16PM 1 LLD: patch to fix libCOFF calling exit() on success in a library function
9:47PM 0 LLD: patch to fix libCOFF calling exit() on success in a library function
9:12PM 1 [RFC] mir-canon: A new tool for canonicalizing MIR for cleaner diffing.
8:54PM 3 [RFC] Value Range Based Optimization Opportunity in LLVM
5:45PM 2 LLD: patch to fix libCOFF calling exit() on success in a library function
2:55PM 0 struct size
2:09PM 5 [RFC] Function stack size section.
1:11PM 2 struct size
11:00AM 0 tsan_interface_java.h; any users? reviving https://github.com/google/java-thread-sanitizer?
10:20AM 1 [cfe-dev] Uncovering non-determinism in LLVM - An Update
9:31AM 2 tsan_interface_java.h; any users? reviving https://github.com/google/java-thread-sanitizer?
5:22AM 0 [5.0.0 Release] Release Candidate 4 tagged
 
Wednesday August 30 2017
TimeRepliesSubject
11:54PM 2 how to auto-report LLVM bugs found by fuzzing?
10:22PM 2 [5.0.0 Release] Release Candidate 4 tagged
9:14PM 1 Register pressure calculation in the machine scheduler and live-through registers
9:14PM 0 [5.0.0 Release] Release Candidate 4 tagged
8:43PM 0 Register pressure calculation in the machine scheduler and live-through registers
8:41PM 0 Women in Compilers & Tools Reception - Registration OPEN!
7:27PM 1 Is the flow "llvm-extract -> llvm-link -> clang++ " supposed to be used in this way? To Extract and Re-insert functions?
7:26PM 0 Is the flow "llvm-extract -> llvm-link -> clang++ " supposed to be used in this way? To Extract and Re-insert functions?
6:53PM 0 Is the flow "llvm-extract -> llvm-link -> clang++ " supposed to be used in this way? To Extract and Re-insert functions?
6:19PM 1 LLVM code coverage build problem - LLVM_BUILD_INSTRUMENTED_COVERAGE
5:38PM 0 [lldb-dev] [5.0.0 Release] Release Candidate 3 tagged
4:51PM 0 [cfe-dev] Uncovering non-determinism in LLVM - An Update
4:24PM 0 tsan_interface_java.h; any users? reviving https://github.com/google/java-thread-sanitizer?
2:54PM 0 compyling python by clang
1:47PM 0 assertion in MachineCopyPropagation::isNopCopy
9:03AM 0 Job openings as a virtual machine backend engineer - Qualcomm (Raleigh, NC)
8:51AM 0 How to migrate PassManager CodeGenPasses for LLVM v6.x?
7:51AM 2 tsan_interface_java.h; any users? reviving https://github.com/google/java-thread-sanitizer?
7:49AM 1 vector instruction
6:24AM 0 [5.0.0 Release] Release Candidate 4 tagged
3:20AM 2 Register pressure calculation in the machine scheduler and live-through registers
2:38AM 0 Mischeduler: Unknown reason for peak register pressure increase
 
Tuesday August 29 2017
TimeRepliesSubject
11:52PM 9 [5.0.0 Release] Release Candidate 4 tagged
11:27PM 0 how to auto-report LLVM bugs found by fuzzing?
11:22PM 2 how to auto-report LLVM bugs found by fuzzing?
11:22PM 2 how to auto-report LLVM bugs found by fuzzing?
11:13PM 0 how to auto-report LLVM bugs found by fuzzing?
10:32PM 3 how to auto-report LLVM bugs found by fuzzing?
10:10PM 5 Is the flow "llvm-extract -> llvm-link -> clang++ " supposed to be used in this way? To Extract and Re-insert functions?
8:24PM 1 Finding what IR component llc assert-fails on
6:45PM 2 Uncovering non-determinism in LLVM - An Update
6:34PM 3 Job openings as a virtual machine backend engineer - Qualcomm (Raleigh, NC)
6:17PM 0 [RFC] mir-canon: A new tool for canonicalizing MIR for cleaner diffing.
5:28PM 0 vector instruction
5:24PM 0 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
5:15PM 0 llvm-mc-[dis]assemble-fuzzer status?
4:30PM 1 alloca function in llvm
4:15PM 3 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
4:08PM 0 Need help with review: configurable register sizes in TableGen
3:21PM 0 ARM - TargetStreamer is null
1:23PM 1 [RFC] 'Review corner' section in LLVM Weekly
12:32PM 0 Shipping LLVM.dll for the C API with the Windows installer.
11:22AM 0 [RFC] 'Review corner' section in LLVM Weekly
9:44AM 2 vector instruction
8:10AM 1 Implict output register allocation in two operands instructions set.
5:18AM 0 Job openings as a virtual machine backend engineer - Qualcomm (Raleigh, NC)
4:36AM 0 Instruction Dependency Information in Register Allocation
 
Monday August 28 2017
TimeRepliesSubject
9:18PM 0 LLVM buildmaster will be updated and restarted in 3 hours
9:02PM 0 CUDA separate compilation
8:42PM 0 [5.0.0 Release] Please write release notes
8:23PM 1 [cfe-dev] [5.0.0 Release] Please write release notes
8:13PM 0 [cfe-dev] [5.0.0 Release] Please write release notes
7:48PM 5 [5.0.0 Release] Please write release notes
7:46PM 0 [5.0.0 Release] Release Candidate 3 source and binaries available
5:19PM 1 [RFC] 'Review corner' section in LLVM Weekly
5:02PM 0 [RFC] 'Review corner' section in LLVM Weekly
4:49PM 2 [RFC] 'Review corner' section in LLVM Weekly
4:00PM 1 Is anyone using still using the python bindings?
3:04PM 0 [RFC] 'Review corner' section in LLVM Weekly
3:02PM 1 [RFC] Injecting new element atomic memory intrinsics into MemIntrinsic class hierarchy
2:45PM 0 LLVM Weekly - #191, Aug 28th 2017
2:26PM 1 Buildbot can't submit results to LNT server
2:24PM 0 Buildbot can't submit results to LNT server
9:04AM 2 Buildbot can't submit results to LNT server
7:46AM 1 [Release-testers] [5.0.0 Release] Release Candidate 3 tagged
7:40AM 1 [Release-testers] [5.0.0 Release] Release Candidate 3 tagged
7:40AM 0 [5.0.0 Release] Release Candidate 3 tagged
7:05AM 0 Getting started with LLVM
5:34AM 0 Is anyone using still using the python bindings?
 
Sunday August 27 2017
TimeRepliesSubject
8:30PM 0 ld.lld on MacOS question
10:43AM 2 [RFC] 'Review corner' section in LLVM Weekly
8:24AM 1 LLD invalid x86_64 Reference Kind
6:21AM 1 [5.0.0 Release] Please write release notes
4:49AM 0 [5.0.0 Release] Please write release notes
3:40AM 1 Error in generating Object Code for implemented assembly vector instructions
12:50AM 0 [RFC] 'Review corner' section in LLVM Weekly
 
Saturday August 26 2017
TimeRepliesSubject
11:01PM 9 [RFC] 'Review corner' section in LLVM Weekly
9:10PM 0 question: preferred alignment vs ABI alignment
8:28PM 1 building release_50 with gcc7.2.0 on MacOS: duplicate symbol llvm::DominatorTreeBase
8:23PM 0 building release_50 with gcc7.2.0 on MacOS: duplicate symbol llvm::DominatorTreeBase
7:47PM 0 Error in generating Object Code for implemented assembly vector instructions
7:31PM 0 Register Allocation and Scheduling Issues
7:18PM 2 building release_50 with gcc7.2.0 on MacOS: duplicate symbol llvm::DominatorTreeBase
6:58PM 0 AVX Scheduling and Parallelism
6:14PM 2 Register Allocation and Scheduling Issues
4:52PM 0 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
4:39PM 2 Job openings as a virtual machine backend engineer - Qualcomm (Raleigh, NC)
2:53PM 1 Building LLVM's fuzzers
2:50PM 1 Unaligned atomic load/store
2:15PM 0 Job openings as a virtual machine backend engineer - Qualcomm (Raleigh, NC)
1:30PM 2 libc implementation for the llvm project
12:52PM 0 Unaligned atomic load/store
12:31PM 2 Unaligned atomic load/store
12:00PM 0 [Release-testers] [5.0.0 Release] Release Candidate 3 tagged
9:31AM 2 Error in generating Object Code for implemented assembly vector instructions
8:57AM 2 Getting started with LLVM
8:46AM 1 Fwd: SIGILL with clang
 
Friday August 25 2017
TimeRepliesSubject
10:52PM 9 [5.0.0 Release] Release Candidate 3 tagged
10:28PM 1 Subtarget Initialization in <ARCH>TargetMachine constructor
8:14PM 2 Job openings as a virtual machine backend engineer - Qualcomm (Raleigh, NC)
8:10PM 0 NVPTX Back-end: relocatable device code support for dynamic parallelism
4:47PM 1 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
4:26PM 3 llvm-mc-[dis]assemble-fuzzer status?
3:51PM 0 llvm-mc-[dis]assemble-fuzzer status?
3:15AM 2 Is anyone using still using the python bindings?
1:43AM 1 Building LLVM's fuzzers
1:30AM 0 Building LLVM's fuzzers
1:05AM 1 [5.0.0 Release] Only 3 release blockers left, please help fix!
12:44AM 3 [5.0.0 Release] Please write release notes
 
Thursday August 24 2017
TimeRepliesSubject
11:51PM 0 [5.0.0 Release] Please write release notes
11:24PM 3 Building LLVM's fuzzers
10:58PM 1 llvm-mc-[dis]assemble-fuzzer status?
10:52PM 0 AArch64 buildbots and PR33972
10:38PM 0 Building LLVM's fuzzers
10:35PM 4 Building LLVM's fuzzers
10:21PM 0 Building LLVM's fuzzers
10:20PM 2 Building LLVM's fuzzers
10:20PM 1 Building LLVM's fuzzers
10:16PM 0 Building LLVM's fuzzers
10:16PM 2 AArch64 buildbots and PR33972
10:10PM 2 Building LLVM's fuzzers
10:07PM 3 Building LLVM's fuzzers
9:59PM 0 llvm-mc-[dis]assemble-fuzzer status?
9:55PM 0 Building LLVM's fuzzers
9:49PM 1 [cfe-dev] [5.0.0 Release] Release Candidate 1 tagged
9:49PM 3 Building LLVM's fuzzers
9:48PM 1 [Release-testers] [5.0.0 Release] Release Candidate 2 tagged
9:40PM 1 Building LLVM's fuzzers
9:38PM 2 llvm-mc-[dis]assemble-fuzzer status?
9:37PM 0 Building LLVM's fuzzers
9:29PM 0 llvm-mc-[dis]assemble-fuzzer status?
8:48PM 0 How do set 'nest' addribute in an indirect call?
8:43PM 2 How do set 'nest' addribute in an indirect call?
7:53PM 0 LLVM development trunk - code coverage - branch coverage missing
7:47PM 3 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
7:04PM 0 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
6:47PM 0 Building LLVM's fuzzers
6:39PM 3 Building LLVM's fuzzers
6:31PM 0 Building LLVM's fuzzers
6:29PM 5 Building LLVM's fuzzers
5:40PM 1 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
2:40PM 0 How do set 'nest' addribute in an indirect call?
12:29PM 1 Invalid Signature of orc::RTDyldObjectLinkingLayer::NotifyLoadedFtor
10:22AM 1 Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
10:20AM 0 Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
9:45AM 0 AArch64 buildbots and PR33972
9:38AM 2 AArch64 buildbots and PR33972
7:31AM 0 JIT Optimization Levels
7:21AM 2 JIT Optimization Levels
6:19AM 1 [Bug 33849] [meta] 5.0.0 Release Blockers
4:19AM 2 llvm-mc-[dis]assemble-fuzzer status?
 
Wednesday August 23 2017
TimeRepliesSubject
10:12PM 0 How to generate Object Code for implemeted assembly vecto instructions
9:54PM 0 RISC-V LLVM status update
9:37PM 0 Subtarget Initialization in <ARCH>TargetMachine constructor
8:35PM 0 How to generate Object Code for implemeted assembly vecto instructions
7:47PM 2 Flang – Fortran front-end and runtime for LLVM
6:45PM 3 Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
5:45PM 2 LLVM development trunk - code coverage - branch coverage missing
5:44PM 0 Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
5:21PM 5 Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
5:15PM 1 Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
5:06PM 0 Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
4:58PM 3 Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
4:35PM 0 Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
4:15PM 2 Subtarget Initialization in <ARCH>TargetMachine constructor
3:18PM 0 [lit] Support for Windows 10 Linux subsystem
10:17AM 1 Linker error with libllvm 4.0 on Debian Stretch ARM
7:59AM 0 Subtarget Initialization in <ARCH>TargetMachine constructor
5:49AM 0 ps4-buildslave1a down 08.23.2017
12:08AM 0 RFC: Resolving TBAA issues
 
Tuesday August 22 2017
TimeRepliesSubject
11:43PM 1 llvm-mc-[dis]assemble-fuzzer status?
11:35PM 0 llvm-mc-[dis]assemble-fuzzer status?
11:34PM 0 llvm-mc-[dis]assemble-fuzzer status?
11:21PM 8 llvm-mc-[dis]assemble-fuzzer status?
10:39PM 2 Subtarget Initialization in <ARCH>TargetMachine constructor
9:54PM 0 llvm-pdbutil status?
9:51PM 2 llvm-pdbutil status?
9:49PM 0 llvm-pdbutil status?
9:45PM 4 llvm-pdbutil status?
9:15PM 3 Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
9:09PM 4 [RFC] mir-canon: A new tool for canonicalizing MIR for cleaner diffing.
8:20PM 0 [5.0.0 Release] Please help fix the remaining blockers (2 days left!)
3:02PM 0 Question about built code size
1:52PM 0 Question about built code size
9:59AM 1 RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends
9:41AM 0 RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends
8:59AM 0 Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
6:45AM 0 [RFC] mir-canon: A new tool for canonicalizing MIR for cleaner diffing.
3:51AM 0 Compile mysql with CFI enabled
 
Monday August 21 2017
TimeRepliesSubject
11:36PM 2 [5.0.0 Release] Please help fix the remaining blockers (2 days left!)
10:50PM 0 Emitting output file information in Debug Info Metadata
10:17PM 2 Emitting output file information in Debug Info Metadata
9:59PM 0 [RFC] Pagerando: Page-granularity code randomization
9:43PM 2 RFC: Resolving TBAA issues
9:19PM 0 RFC: Resolving TBAA issues
5:53PM 0 LLVM Weekly - #190, Aug 21st 2017
5:23PM 0 Optimization Remark Emitter API
5:12PM 0 [RFC] Injecting new element atomic memory intrinsics into MemIntrinsic class hierarchy
4:18PM 0 Vectorization in LLVM x86 backend
4:14PM 2 Vectorization in LLVM x86 backend
3:56PM 0 Vectorization in LLVM x86 backend
3:49PM 2 Vectorization in LLVM x86 backend
2:57PM 2 [RFC] Injecting new element atomic memory intrinsics into MemIntrinsic class hierarchy
2:32PM 3 RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends
12:23PM 2 Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
10:58AM 1 Flang - How to collaborate best
10:53AM 0 RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends
10:42AM 0 DragonEgg for GCC v8.x and LLVM v6.x is just able to work
10:06AM 4 RISC-V LLVM status update
7:25AM 0 Combining passes
7:09AM 1 Vectorization in LLVM x86 backend
6:17AM 2 Combining passes
3:31AM 3 DragonEgg for GCC v8.x and LLVM v6.x is just able to work
1:47AM 2 RFC: Resolving TBAA issues
 
Sunday August 20 2017
TimeRepliesSubject
7:13PM 0 Out Of Memory when compiling complex template in C++
6:30PM 1 RFC: Resolving TBAA issues
6:22PM 0 RFC: Resolving TBAA issues
5:49PM 1 llvm-symbolizer.test and %T
5:11PM 0 RFC: Resolving TBAA issues
5:02PM 5 RFC: Resolving TBAA issues
4:31PM 0 RFC: Resolving TBAA issues
4:27PM 3 RFC: Resolving TBAA issues
4:22PM 0 RFC: Resolving TBAA issues
4:22PM 0 Alloca in AS3 and the NVPTX backend
4:16PM 2 RFC: Resolving TBAA issues
3:54PM 0 RFC: Resolving TBAA issues
3:40PM 3 Out Of Memory when compiling complex template in C++
2:49PM 2 RFC: Resolving TBAA issues
2:11PM 1 RFC: Resolving TBAA issues
9:47AM 0 RFC: Resolving TBAA issues
8:17AM 1 [Release-testers] [5.0.0 Release] Release Candidate 2 source and binaries available
7:47AM 3 Buildmaster restart 08.20.2017
2:00AM 0 [5.0.0 Release] Release Candidate 2 source and binaries available
 
Saturday August 19 2017
TimeRepliesSubject
8:36PM 4 RFC: Resolving TBAA issues
8:13PM 0 [RFC] Injecting new element atomic memory intrinsics into MemIntrinsic class hierarchy
8:04PM 0 RFC: Resolving TBAA issues
7:33PM 0 RFC: Resolving TBAA issues
7:05PM 2 RFC: Resolving TBAA issues
7:00PM 0 RFC: Resolving TBAA issues
6:32PM 0 [cfe-dev] Which is the best compiler to build LLVM 5.0.0 rc2?
6:27PM 0 RFC: Resolving TBAA issues
6:08PM 2 RFC: Resolving TBAA issues
6:00PM 2 RFC: Resolving TBAA issues
5:58PM 0 RFC: Resolving TBAA issues
5:54PM 0 RFC: Resolving TBAA issues
5:48PM 2 RFC: Resolving TBAA issues
4:28PM 2 RFC: Resolving TBAA issues
4:00PM 1 Which is the best compiler to build LLVM 5.0.0 rc2?
4:00PM 0 RFC: Resolving TBAA issues
1:29PM 3 RFC: Resolving TBAA issues
 
Friday August 18 2017
TimeRepliesSubject
11:08PM 2 [5.0.0 Release] Please write release notes
10:58PM 0 An update on the DominatorTree and incremental dominators
6:37PM 1 Hoisting convergent function calls
3:44PM 0 [lldb-dev] [5.0.0 Release] Release Candidate 2 source and binaries available
2:53PM 0 RFC: Resolving TBAA issues
2:48PM 0 RFC: Resolving TBAA issues
2:24PM 1 RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends
1:10PM 0 RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends
12:02PM 2 RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends
10:05AM 0 RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends
9:55AM 5 RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends
4:25AM 2 RFC: Resolving TBAA issues
3:15AM 0 RFC: Resolving TBAA issues
12:35AM 2 [GreenDragon] Jenkins Core and Plugin Maintenance
12:20AM 2 RFC: Resolving TBAA issues
12:11AM 2 RFC: Resolving TBAA issues
 
Thursday August 17 2017
TimeRepliesSubject
11:49PM 0 RFC: Resolving TBAA issues
11:03PM 0 [5.0.0 Release] Release Candidate 2 tagged
10:15PM 3 How do set 'nest' addribute in an indirect call?
9:49PM 4 RFC: Resolving TBAA issues
9:03PM 1 ps4-buildslave2 will be disconnected from master
8:09PM 0 [cfe-dev] Disable memset synthesis
7:28PM 0 unable to emit vectorized code in LLVM IR
7:21PM 2 unable to emit vectorized code in LLVM IR
7:17PM 0 unable to emit vectorized code in LLVM IR
7:12PM 2 unable to emit vectorized code in LLVM IR
7:01PM 1 Inst->replaceAllUsesWith and uses in ConstantExpr
6:51PM 0 unable to emit vectorized code in LLVM IR
6:51PM 0 unable to emit vectorized code in LLVM IR
6:44PM 4 unable to emit vectorized code in LLVM IR
6:37PM 0 unable to emit vectorized code in LLVM IR
5:56PM 3 [cfe-dev] Disable memset synthesis
5:28PM 0 [cfe-dev] Disable memset synthesis
5:10PM 0 unable to emit vectorized code in LLVM IR
5:09PM 2 unable to emit vectorized code in LLVM IR
5:03PM 0 unable to emit vectorized code in LLVM IR
5:02PM 0 reg coalescing improvements
5:01PM 4 unable to emit vectorized code in LLVM IR
4:57PM 0 unable to emit vectorized code in LLVM IR
4:52PM 3 unable to emit vectorized code in LLVM IR
4:49PM 1 A problem with register allocator
4:24PM 0 High Performance containers
3:49PM 1 Missing some cross iteration memory dependencies for software pipeline?
3:32PM 3 [RFC] Injecting new element atomic memory intrinsics into MemIntrinsic class hierarchy
3:16PM 0 High Performance containers
2:50PM 3 High Performance containers
2:35PM 0 LLD/COFF Trying to link very old .lib files
2:27PM 0 High Performance containers
2:08PM 1 callee saved regs list
1:48PM 1 LLVM JIT Compilation
1:48PM 0 callee saved regs list
12:47PM 0 Backend for Instruction List (IL) according to 61131-3
12:34PM 2 High Performance containers
12:21PM 1 Storing and loading of i1
12:08PM 0 High Performance containers
11:54AM 0 High Performance containers
11:39AM 2 High Performance containers
10:52AM 2 reg coalescing improvements
10:19AM 1 Cambridge LLVM Social, Aug 23rd
10:07AM 3 callee saved regs list
8:23AM 0 High Performance containers
8:22AM 0 Inst->replaceAllUsesWith and uses in ConstantExpr
8:17AM 0 LLVM Weekly - #189, Aug 14th 2017
6:53AM 3 Inst->replaceAllUsesWith and uses in ConstantExpr
5:44AM 0 unable to emit vectorized code in LLVM IR
12:12AM 0 Inst->replaceAllUsesWith and uses in ConstantExpr
12:01AM 2 Inst->replaceAllUsesWith and uses in ConstantExpr
 
Wednesday August 16 2017
TimeRepliesSubject
11:05PM 0 Inst->replaceAllUsesWith and uses in ConstantExpr
10:39PM 2 Inst->replaceAllUsesWith and uses in ConstantExpr
10:28PM 3 CUDA separate compilation
9:38PM 2 unable to emit vectorized code in LLVM IR
8:55PM 0 LLVM JIT Compilation
7:57PM 0 LLVM JIT Compilation
7:05PM 3 LLVM JIT Compilation
6:59PM 0 RFC: Resolving TBAA issues
5:49PM 0 LLVM JIT Compilation
5:38PM 2 [cfe-dev] Disable memset synthesis
5:05PM 1 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
4:55PM 0 Heroic LLVM optimizations
4:37PM 1 Heroic LLVM optimizations
4:34PM 0 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
1:27PM 1 LoopVectorize - determine the bounds of the original loop
10:44AM 1 add/sub instructions
10:24AM 4 High Performance containers
8:22AM 1 Disable memset synthesis
5:07AM 0 Heroic LLVM optimizations
5:06AM 2 Heroic LLVM optimizations
4:39AM 0 Heroic LLVM optimizations
4:37AM 0 Disable memset synthesis
2:38AM 3 Disable memset synthesis
 
Tuesday August 15 2017
TimeRepliesSubject
11:26PM 0 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
11:22PM 2 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
11:14PM 0 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
10:15PM 2 Heroic LLVM optimizations
10:09PM 0 lldb-amd64-ninja-netbsd7 builder
9:36PM 0 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
8:14PM 3 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
7:06PM 4 [RFC] mir-canon: A new tool for canonicalizing MIR for cleaner diffing.
6:45PM 0 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
6:33PM 1 [XRay] Alternatives to relocations in .text section
6:22PM 8 [RFC] Enhance Partial Inliner by using a general outlining scheme for cold blocks
6:05PM 0 transfer type to 'local' context
4:59PM 0 [XRay] Alternatives to relocations in .text section
2:17PM 1 ORC JIT compilation - can I recover the size of the generated function?
1:43PM 2 -Rpass-missed vs -Rpass-analysis
1:05PM 0 Problem of getting two unused registers in eliminateFrameIndex()
12:48PM 2 transfer type to 'local' context
12:47PM 1 How to debug instruction selection
12:44PM 0 How to debug instruction selection
9:37AM 3 [XRay] Alternatives to relocations in .text section
7:58AM 3 How to debug instruction selection
3:28AM 0 [ScalarEvolution][SCEV] no-wrap flags dependent on order of getSCEV() calls
1:39AM 2 Problem of getting two unused registers in eliminateFrameIndex()
 
Monday August 14 2017
TimeRepliesSubject
11:15PM 1 [PATCH v2 0/2] clang-format
10:52PM 2 [ScalarEvolution][SCEV] no-wrap flags dependent on order of getSCEV() calls
10:30PM 4 [5.0.0 Release] Release Candidate 2 source and binaries available
8:12PM 0 [RFC] The future of the va_arg instruction
7:57PM 0 Mischeduler: Unknown reason for peak register pressure increase
6:55PM 1 Removing the 'Time Estimate Box' from bugzilla UI
6:49PM 1 PHI incoming blocks order
6:47PM 0 PHI incoming blocks order
6:37PM 2 LLVM Weekly - #189, Aug 14th 2017
5:29PM 4 RFC: Representing unions in TBAA
5:10PM 0 RFC: Representing unions in TBAA
5:04PM 2 RFC: Representing unions in TBAA
4:58PM 0 RFC: Representing unions in TBAA
3:27PM 1 Apple radar references in the LLDB test suite
2:44PM 0 Buildmaster reconfig
2:35PM 0 [ScalarEvolution][SCEV] no-wrap flags dependent on order of getSCEV() calls
1:07PM 1 reg alloc hints
12:09PM 0 clang-tidy : Modify cert-err60-cpp configuration
11:39AM 1 InstCombine GEP
10:58AM 4 PHI incoming blocks order
10:36AM 0 [Release-testers] [5.0.0 Release] Release Candidate 2 tagged
10:34AM 2 clang-tidy : Modify cert-err60-cpp configuration
9:26AM 2 [RFC] The future of the va_arg instruction
6:48AM 0 PHI nodes and connected ICMp
5:36AM 2 [ScalarEvolution][SCEV] no-wrap flags dependent on order of getSCEV() calls
5:24AM 0 InstCombine GEP
3:00AM 2 PHI nodes and connected ICMp
 
Sunday August 13 2017
TimeRepliesSubject
4:46PM 0 ind variable
12:58PM 0 PHI nodes and connected ICMp
12:55PM 2 PHI nodes and connected ICMp
10:57AM 2 How do I generate a combined .ll file from makefile or configure file?
10:40AM 1 Relicensing: Revised Developer Policy
 
Saturday August 12 2017
TimeRepliesSubject
6:26PM 0 LLVM-4.0.1 build problem on Linux
2:40PM 1 Converting i32** to [4 x i32]* ?
2:32PM 0 Converting i32** to [4 x i32]* ?
11:13AM 2 Converting i32** to [4 x i32]* ?
5:56AM 3 Mischeduler: Unknown reason for peak register pressure increase
5:37AM 1 [Release-testers] [5.0.0 Release] Release Candidate 2 tagged
12:36AM 0 [Release-testers] [5.0.0 Release] Release Candidate 2 tagged
 
Friday August 11 2017
TimeRepliesSubject
11:44PM 2 [Release-testers] [5.0.0 Release] Release Candidate 2 tagged
9:54PM 0 [Release-testers] [5.0.0 Release] Release Candidate 2 tagged
9:47PM 0 Converting i32** to [4 x i32]* ?
8:49PM 1 Relicensing: Revised Developer Policy
8:40PM 2 Converting i32** to [4 x i32]* ?
8:07PM 0 Relicensing: Revised Developer Policy
6:45PM 1 BranchProbability/BlockFrequency for a chain of ifs
6:37PM 0 Are SCEV normal form?
6:31PM 0 BranchProbability/BlockFrequency for a chain of ifs
6:18PM 0 llvmlite pass manager
5:17PM 2 Are SCEV normal form?
4:57PM 0 Are SCEV normal form?
4:14PM 2 LLVM-4.0.1 build problem on Linux
4:02PM 1 Relicensing: Revised Developer Policy
1:56PM 0 PHI nodes and connected ICMp
1:55PM 2 PHI nodes and connected ICMp
11:59AM 1 LLVM (Cool/Warm) DOT Printers for Profiling
8:41AM 0 Entry and Shared Machine Basic Blocks of a Machine Function
6:10AM 0 Want to write a static code analysis tool to locate all possible dangling pointer in c++ code
2:00AM 9 [5.0.0 Release] Release Candidate 2 tagged
1:45AM 1 Is anyone experienced writing Sphinx documentation?
1:42AM 0 Is anyone experienced writing Sphinx documentation?
1:20AM 1 Compile issues with LLVM ORC JIT
12:29AM 0 Relicensing: Revised Developer Policy
 
Thursday August 10 2017
TimeRepliesSubject
11:46PM 2 Is anyone experienced writing Sphinx documentation?
11:32PM 0 LLVM (Cool/Warm) DOT Printers for Profiling
11:14PM 0 Test Error Paths for Expected & ErrorOr
10:13PM 5 Relicensing: Revised Developer Policy
10:08PM 0 Relicensing: Revised Developer Policy
10:03PM 3 Relicensing: Revised Developer Policy
9:59PM 0 Relicensing: Revised Developer Policy
9:57PM 1 Weird miscompilation? Please help, i'm lost.
9:22PM 0 Keys used to sign releases
8:54PM 2 Relicensing: Revised Developer Policy
8:05PM 0 Relicensing: Revised Developer Policy
7:32PM 1 sinking in LICM
7:02PM 0 [cfe-dev] How Pragma Unroll works in clang and llvm
6:55PM 0 sinking in LICM
6:52PM 0 Custom call lowering - where?
6:42PM 0 sinking in LICM
6:34PM 4 sinking in LICM
6:25PM 0 Custom call lowering - where?
5:58PM 3 InstCombine GEP
5:30PM 0 PHI nodes and connected ICMp
5:24PM 0 InstCombine GEP
3:53PM 2 Relicensing: Revised Developer Policy
3:33PM 0 Relicensing: Revised Developer Policy
9:52AM 1 llvm-5.0: couldn't build libomptarget
8:59AM 0 [poison] re: is select-of-select to logic+select allowed ?
8:49AM 1 Custom call lowering - where?
8:00AM 0 PHI nodes and connected ICMp
7:55AM 4 PHI nodes and connected ICMp
7:47AM 0 PHI nodes and connected ICMp
7:39AM 1 [ThinLTO] Suggestions on how to traverse SCCs in the Module Summary Index bottom up
7:34AM 2 PHI nodes and connected ICMp
7:22AM 4 InstCombine GEP
4:27AM 0 Staging buildmaster down?
3:57AM 2 Keys used to sign releases
 
Wednesday August 9 2017
TimeRepliesSubject
10:04PM 0 [ThinLTO] Suggestions on how to traverse SCCs in the Module Summary Index bottom up
8:02PM 0 test-suite: SPEC CPU 2017
7:27PM 0 Improving SCEV's behavior around IR level no-wrap
7:22PM 0 [cfe-dev] [5.0.0 Release] Release Candidate 1 tagged
7:14PM 0 Target mistakenly added to `LLVM_ALL_TARGETS` (RISCV)
7:12PM 2 test-suite: SPEC CPU 2017
6:38PM 0 [RFC] The future of the va_arg instruction
6:38PM 0 Can a Constant have more than one use?
6:28PM 0 LLVM-HPC2017 Workshop at SC17 - Call for papers
6:23PM 2 Can a Constant have more than one use?
6:18PM 1 What constitutes a replaceable use?
4:11PM 4 [RFC] The future of the va_arg instruction
3:58PM 0 [ScalarEvolution][SCEV] no-wrap flags dependent on order of getSCEV() calls
3:07PM 0 [5.0.0 Release] Release Candidate 1 tagged
2:21PM 2 [ThinLTO] Suggestions on how to traverse SCCs in the Module Summary Index bottom up
12:57PM 1 ind variable
12:51PM 0 ind variable
12:44PM 0 Open Position - Compilation for Heterogenous Systems (FPGA, Math. Optimization, Polyhedral Compilation)
12:33PM 0 Dependence analysis - missing loop-carried dependencies?
12:28PM 4 ind variable
12:23PM 0 ind variable
12:18PM 2 ind variable
3:29AM 2 Improving SCEV's behavior around IR level no-wrap
12:38AM 2 [ScalarEvolution][SCEV] no-wrap flags dependent on order of getSCEV() calls
12:34AM 0 Improving SCEV's behavior around IR level no-wrap
12:02AM 1 Getting rid of "%T" expansions
 
Tuesday August 8 2017
TimeRepliesSubject
10:06PM 2 Improving SCEV's behavior around IR level no-wrap
7:58PM 0 [ScalarEvolution][SCEV] no-wrap flags dependent on order of getSCEV() calls
7:17PM 2 [ScalarEvolution][SCEV] no-wrap flags dependent on order of getSCEV() calls
5:49PM 0 DWARF: Ranges base address specifier entries & Gold's gdb-index 32 bit bug
5:43PM 0 Safety of changing values of variables by editing CMakeCache.txt Vs supplying them through the command line
5:37PM 0 [ScalarEvolution][SCEV] no-wrap flags dependent on order of getSCEV() calls
5:32PM 2 Safety of changing values of variables by editing CMakeCache.txt Vs supplying them through the command line
5:22PM 2 [ScalarEvolution][SCEV] no-wrap flags dependent on order of getSCEV() calls
4:20PM 0 Tuning CSRCost for shrink-wrapping
3:21PM 0 [RFC][InlineCost] Modeling JumpThreading (or similar) in inline cost model
2:59PM 2 DWARF: Ranges base address specifier entries & Gold's gdb-index 32 bit bug
2:43PM 0 DWARF: Ranges base address specifier entries & Gold's gdb-index 32 bit bug
2:41PM 2 DWARF: Ranges base address specifier entries & Gold's gdb-index 32 bit bug
1:56PM 0 DWARF: Ranges base address specifier entries & Gold's gdb-index 32 bit bug
1:32PM 0 DWARF: Ranges base address specifier entries & Gold's gdb-index 32 bit bug
12:32PM 0 ETA on previous Dev. Mtg. videos becoming available
12:10PM 0 dump
12:03PM 2 dump
9:14AM 1 vrp
7:40AM 0 Compile issues with LLVM ORC JIT
6:53AM 1 Relicensing: Revised Developer Policy
6:48AM 0 Relicensing: Revised Developer Policy
3:24AM 0 AliasAnalysis: may-alias subcategory
 
Monday August 7 2017
TimeRepliesSubject
11:13PM 0 [LNT] new server instance http://lnt.llvm.org seems unstable
10:58PM 4 DWARF: Ranges base address specifier entries & Gold's gdb-index 32 bit bug
10:09PM 0 [Job Ad] Compiler Engineer working on Systems Security
9:29PM 2 [RFC][InlineCost] Modeling JumpThreading (or similar) in inline cost model
6:12PM 0 VBROADCAST Implementation Issues
5:57PM 0 VBROADCAST Implementation Issues
5:49PM 1 Advise to implement return barriar
5:37PM 0 VBROADCAST Implementation Issues
5:19PM 3 VBROADCAST Implementation Issues
5:02PM 0 [RFC][InlineCost] Modeling JumpThreading (or similar) in inline cost model
4:44PM 0 Re-computing Live-in/Live-out Physical Registers for Basic Blocks Using LivePhysRegs
4:01PM 1 Detect auto vectorization in LLVM IR
3:53PM 6 Relicensing: Revised Developer Policy
3:50PM 0 LLVM Weekly - #188, Aug 7th 2017
3:28PM 3 AliasAnalysis: may-alias subcategory
2:56PM 3 [RFC][InlineCost] Modeling JumpThreading (or similar) in inline cost model
2:54PM 0 LLVM Compiler Social Zurich - August 10, 2017
2:04PM 1 fatal error: clang/Basic/Version.inc: No such file or directory
12:51PM 0 Call for Talks, Tutorials, BoFs, Panels, Student Research Competition, and More!
12:42PM 0 AliasAnalysis: may-alias subcategory
11:29AM 2 AliasAnalysis: may-alias subcategory
10:38AM 0 vrp
10:05AM 2 vrp
9:41AM 0 vrp
9:34AM 2 vrp
9:14AM 0 vrp
9:12AM 2 vrp
8:54AM 1 VBROADCAST Implementation Issues
8:20AM 0 VBROADCAST Implementation Issues
8:13AM 2 VBROADCAST Implementation Issues
4:17AM 0 fatal error: clang/Basic/Version.inc: No such file or directory
 
Sunday August 6 2017
TimeRepliesSubject
9:57PM 0 VBROADCAST Implementation Issues
9:36PM 0 VGATHER Implementation Issues
9:21PM 2 VBROADCAST Implementation Issues
8:43PM 0 LLVM Vectorisation Bug
7:03PM 0 VBROADCAST Implementation Issues
4:35PM 2 Compile issues with LLVM ORC JIT
2:11AM 2 Staging buildmaster down?
1:03AM 1 LLVM build failures of Sanitized builds
 
Saturday August 5 2017
TimeRepliesSubject
9:47PM 1 Cross compiling C++ program
9:40PM 0 Phabricator "O<n>" link expansion.
7:24PM 0 VBROADCAST Implementation Issues
6:40PM 0 LLVM build failures of Sanitized builds
5:55PM 2 LLVM Vectorisation Bug
5:50PM 0 VBROADCAST Implementation Issues
5:39PM 1 3 stage ninja bootstrap on darwin?
3:20PM 1 [GreenDragon] Jenkins Plugin maintenance
2:19PM 0 Cross compiling C++ program
2:03PM 0 Legalize sdiv Instruction for vector integer
1:41PM 3 Cross compiling C++ program
12:27PM 0 Bug or incorrect use of inline asm?
5:45AM 0 Buildmaster restart
5:28AM 0 Compile LLVM into LLVM IR with non-Xcode Clang
4:15AM 0 [RFC] Profile guided section layout
3:48AM 0 llvm-dev Digest, Vol 158, Issue 27
3:25AM 0 Missing videos from old dev mtgs
2:25AM 1 BranchProbability/BlockFrequency for a chain of ifs
2:14AM 0 BranchProbability/BlockFrequency for a chain of ifs
 
Friday August 4 2017
TimeRepliesSubject
11:45PM 0 cannot build CUDA support with llvm-trunk
11:10PM 4 BranchProbability/BlockFrequency for a chain of ifs
10:40PM 0 Cross compiling C++ program
10:29PM 3 Cross compiling C++ program
10:07PM 0 [RFC][InlineCost] Modeling JumpThreading (or similar) in inline cost model
10:03PM 0 Cross compiling C++ program
9:50PM 2 Cross compiling C++ program
9:34PM 0 Cross compiling C++ program
9:04PM 3 Cross compiling C++ program
7:54PM 0 Cross compiling C++ program
7:14PM 3 Cross compiling C++ program
6:55PM 0 [RFC][InlineCost] Modeling JumpThreading (or similar) in inline cost model
6:41PM 4 [RFC][InlineCost] Modeling JumpThreading (or similar) in inline cost model
6:23PM 0 Adding new fields to bugzilla
6:14PM 1 [RFC] Adding ARC backend
6:06PM 0 [RFC][InlineCost] Modeling JumpThreading (or similar) in inline cost model
6:03PM 0 GEP with a null pointer base
5:55PM 0 Adding new fields to bugzilla
5:39PM 1 [Release-testers] [cfe-dev] [5.0.0 Release] Release Candidate 1 tagged
3:56PM 3 [RFC][InlineCost] Modeling JumpThreading (or similar) in inline cost model
2:20PM 0 Status of llvm.experimental.vector.reduce.* intrinsics
2:03PM 3 Status of llvm.experimental.vector.reduce.* intrinsics
1:57PM 0 Status of llvm.experimental.vector.reduce.* intrinsics
1:55PM 2 Status of llvm.experimental.vector.reduce.* intrinsics
1:08PM 0 [Release-testers] [cfe-dev] [5.0.0 Release] Release Candidate 1 tagged
12:42PM 2 LLVM build failures of Sanitized builds
12:40PM 1 Continuing: How to write a custom LTO pass?
12:36PM 1 Status of llvm.experimental.vector.reduce.* intrinsics
11:11AM 1 cannot build CUDA support with llvm-trunk
10:04AM 0 FYI: Ninja-build user may use CMake-3.9
9:55AM 2 Bug or incorrect use of inline asm?
9:33AM 1 [cfe-dev] [5.0.0 Release] Release Candidate 1 tagged
6:18AM 0 Status of llvm.experimental.vector.reduce.* intrinsics
 
Thursday August 3 2017
TimeRepliesSubject
11:51PM 0 [cfe-dev] [5.0.0 Release] Release Candidate 1 tagged
10:48PM 2 Status of llvm.experimental.vector.reduce.* intrinsics
10:19PM 1 A CFG issue
9:54PM 0 [RFC][GlobalISel] Making GlobalISel non-optional in the build
5:23PM 1 Why LLVM doesn't have debug information of function right parentheses?
4:19PM 0 Bug or incorrect use of inline asm?
4:10PM 1 Why LLVM doesn't have debug information of function right parentheses?
3:58PM 4 Bug or incorrect use of inline asm?
3:21PM 0 Why LLVM doesn't have debug information of function right parentheses?
3:05PM 3 Why LLVM doesn't have debug information of function right parentheses?
2:57PM 2 Dependence analysis - missing loop-carried dependencies?
2:22PM 0 Cross compiling C++ program
2:13PM 0 Why LLVM doesn't have debug information of function right parentheses?
1:02PM 1 LLVM-IR: order of a PHI node predecessors ?
12:49PM 0 Status of llvm.experimental.vector.reduce.* intrinsics
11:47AM 2 fatal error: clang/Basic/Version.inc: No such file or directory
11:03AM 2 Status of llvm.experimental.vector.reduce.* intrinsics
4:11AM 2 [LNT] new server instance http://lnt.llvm.org seems unstable
4:03AM 0 Buildmaster restart
3:19AM 2 Why LLVM doesn't have debug information of function right parentheses?
2:20AM 2 Re-computing Live-in/Live-out Physical Registers for Basic Blocks Using LivePhysRegs
 
Wednesday August 2 2017
TimeRepliesSubject
11:57PM 2 Cross compiling C++ program
11:48PM 0 Cross compiling C++ program
11:40PM 0 [InstCombine] Simplification sometimes only transforms but doesn't simplify instruction, causing side effect in other pass
11:35PM 1 RFC] Shrink-wrapping improvement
11:29PM 2 [InstCombine] Simplification sometimes only transforms but doesn't simplify instruction, causing side effect in other pass
11:28PM 2 Cross compiling C++ program
11:28PM 1 can llvm-lit pass output of one RUN command as an argument to another RUN command
11:22PM 0 can llvm-lit pass output of one RUN command as an argument to another RUN command
11:07PM 0 [InstCombine] Simplification sometimes only transforms but doesn't simplify instruction, causing side effect in other pass
11:06PM 2 can llvm-lit pass output of one RUN command as an argument to another RUN command
11:00PM 3 [InstCombine] Simplification sometimes only transforms but doesn't simplify instruction, causing side effect in other pass
10:50PM 0 A CFG issue
10:45PM 0 CUDA compilation "No available targets are compatible with this triple." problem
10:36PM 0 [InstCombine] Simplification sometimes only transforms but doesn't simplify instruction, causing side effect in other pass
10:00PM 3 [InstCombine] Simplification sometimes only transforms but doesn't simplify instruction, causing side effect in other pass
9:22PM 1 Efficiently ignoring upper 32 pointer bits whendereferencing
9:17PM 0 Efficiently ignoring upper 32 pointer bits whendereferencing
9:03PM 2 Efficiently ignoring upper 32 pointer bits whendereferencing
8:21PM 1 libFuzzer: add an option to always null-terminate?
8:12PM 2 CUDA compilation "No available targets are compatible with this triple." problem
7:55PM 0 [LNT] new server instance http://lnt.llvm.org seems unstable
7:51PM 2 [LNT] new server instance http://lnt.llvm.org seems unstable
7:49PM 0 [LNT] new server instance http://lnt.llvm.org seems unstable
7:47PM 0 [LNT] new server instance http://lnt.llvm.org seems unstable
7:46PM 2 [LNT] new server instance http://lnt.llvm.org seems unstable
7:45PM 0 [LNT] new server instance http://lnt.llvm.org seems unstable
7:45PM 2 [LNT] new server instance http://lnt.llvm.org seems unstable
7:44PM 0 CUDA compilation "No available targets are compatible with this triple." problem
7:43PM 0 [LNT] new server instance http://lnt.llvm.org seems unstable
7:42PM 0 libFuzzer: add an option to always null-terminate?
7:24PM 2 libFuzzer: add an option to always null-terminate?
6:49PM 0 LLVM's loop strength reduction module
6:48PM 0 ubsan no longer compiles when libc++ is the default
6:23PM 2 CUDA compilation "No available targets are compatible with this triple." problem
5:47PM 0 Efficiently ignoring upper 32 pointer bits when dereferencing
5:37PM 0 LLVM's loop strength reduction module
4:03PM 2 Efficiently ignoring upper 32 pointer bits when dereferencing
3:52PM 0 llvm-trunk errors with gcc-5.3.0 on SuSE Linux
3:47PM 1 Making a pointer parameter always dereferenceable
3:31PM 2 Lab is down
2:58PM 0 GEP with a null pointer base
2:02PM 1 GEP with a null pointer base
1:29PM 1 GEP with a null pointer base
10:18AM 1 segmentation fault compiling program with OpenMP pragmas
9:45AM 1 Re-computing Live-in/Live-out Physical Registers for Basic Blocks Using LivePhysRegs
8:47AM 2 ubsan no longer compiles when libc++ is the default
6:44AM 2 llvm-trunk errors with gcc-5.3.0 on SuSE Linux
6:13AM 0 [Openmp-dev] [cfe-dev] [Release-testers] [5.0.0 Release] Release Candidate 1 tagged
12:19AM 0 GEP with a null pointer base
 
Tuesday August 1 2017
TimeRepliesSubject
11:17PM 0 GEP with a null pointer base
9:29PM 0 [RFC][Dominators] Batch update API for dominators
9:25PM 1 [RFC] Profile guided section layout
9:10PM 0 How to directly annotate the content a pointer points to in Clang?
8:57PM 0 [RFC] Profile guided section layout
8:03PM 1 [RFC] Add IR level interprocedural outliner for code size.
7:42PM 2 intrinsics
7:28PM 0 [RFC] Add IR level interprocedural outliner for code size.
7:20PM 0 [RFC] Add IR level interprocedural outliner for code size.
7:01PM 2 [RFC] Add IR level interprocedural outliner for code size.
6:35PM 0 [RFC] Add IR level interprocedural outliner for code size.
6:20PM 2 [RFC] Add IR level interprocedural outliner for code size.
6:03PM 0 [RFC] Add IR level interprocedural outliner for code size.
5:44PM 0 [RFC] Add IR level interprocedural outliner for code size.
5:32PM 0 ubsan no longer compiles when libc++ is the default
5:28PM 7 [RFC] Add IR level interprocedural outliner for code size.
5:15PM 0 lld/win32 creates pic code for threadlocal
5:12PM 0 Tail merging "undef" with a defined register: wrong code
5:08PM 1 Making an analysis availble during call lowering
4:51PM 0 Making an analysis availble during call lowering
4:36PM 0 X86PadShortFunction.cpp inserts noops twice
4:15PM 0 [RFC] Add IR level interprocedural outliner for code size.
4:13PM 3 [cfe-dev] [5.0.0 Release] Release Candidate 1 tagged
3:22PM 1 [HELP] Segfault on printing out structure elements
2:07PM 2 ubsan no longer compiles when libc++ is the default
11:47AM 0 Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register
11:39AM 0 Reported bugs in clang-format and clang-tidy
11:03AM 0 ISelDAGToDAG breaks node ordering
10:35AM 0 Disassembler/InstPrinter problem with implict output register.
10:01AM 0 [cfe-dev] [5.0.0 Release] Release Candidate 1 tagged
9:53AM 0 [RFC] Add IR level interprocedural outliner for code size.
9:01AM 0 How to migrate Target option PositionIndependentExecutable for LLVM v3.9?
8:17AM 4 [RFC] Add IR level interprocedural outliner for code size.
8:07AM 0 [RFC] Add IR level interprocedural outliner for code size.
8:04AM 2 X86PadShortFunction.cpp inserts noops twice
8:02AM 0 [RFC] Add IR level interprocedural outliner for code size.
7:35AM 0 armv7 pc-rel bx thumb instruction
5:38AM 7 [RFC] Add IR level interprocedural outliner for code size.
5:00AM 2 Making an analysis availble during call lowering
4:47AM 1 Making an analysis availble during call lowering
3:39AM 0 [RFC] Profile guided section layout
1:08AM 0 [DevTool] LLVM executable/pass project template generator
12:26AM 1 [RFC] Profile guided section layout