llvm dev - Jul 2017

Monday July 31 2017
TimeRepliesSubject
11:45PM 1 [cfe-dev] [5.0.0 Release] Release Candidate 1 tagged
11:36PM 0 [5.0.0 Release] Release Candidate 1 source and binaries available
11:20PM 1 AsmPrinter.cpp: emitting trailing padding for global data array in emitGlobalConstantDataSequential
11:04PM 0 August LLVM bay-area social is this Thursday!
10:39PM 1 X86 Backend SelectionDAG - Source Scheduling
10:36PM 1 X86 Backend SelectionDAG - Source Scheduling
10:33PM 2 [LNT] new server instance http://lnt.llvm.org seems unstable
10:24PM 1 X86 Backend SelectionDAG - Source Scheduling
10:19PM 2 [RFC] Profile guided section layout
10:12PM 1 [RFC] Profile guided section layout
10:11PM 2 [RFC] Profile guided section layout
9:51PM 1 X86 Backend SelectionDAG - Source Scheduling
9:43PM 1 [RFC] Profile guided section layout
9:20PM 5 [RFC] Profile guided section layout
8:55PM 1 lldb-amd64-ninja-netbsd7 builder
8:55PM 1 RTTI with smart pointers
8:09PM 1 Internal server error when submitting LNT to lnt.llvm.org
8:02PM 1 Internal server error when submitting LNT to lnt.llvm.org
7:31PM 1 Making an analysis availble during call lowering
7:26PM 1 ISelDAGToDAG breaks node ordering
6:29PM 0 LLVM Weekly - #187, Jul 31st 2017
6:13PM 2 [cfe-dev] [5.0.0 Release] Release Candidate 1 tagged
5:26PM 1 [cfe-dev] [5.0.0 Release] Release Candidate 1 tagged
5:12PM 1 [RFC] Add IR level interprocedural outliner for code size.
4:57PM 1 [RFC] Add IR level interprocedural outliner for code size.
4:48PM 5 GEP with a null pointer base
3:55PM 1 [cfe-dev] [Release-testers] [5.0.0 Release] Release Candidate 1 tagged
3:53PM 2 Test Error Paths for Expected & ErrorOr
3:46PM 1 [RFC] Add IR level interprocedural outliner for code size.
3:19PM 1 Test Error Paths for Expected & ErrorOr
12:43PM 1 RTTI with smart pointers
12:30PM 1 [SPIR-V] SPIR-V in LLVM
11:37AM 1 Internal server error when submitting LNT to lnt.llvm.org
11:29AM 1 No email notifications from Phabricator
9:02AM 1 unsigned operations with negative numbers
8:56AM 3 unsigned operations with negative numbers
8:15AM 2 LLVM's loop strength reduction module
7:10AM 1 [LNT] new server instance http://lnt.llvm.org seems unstable
1:34AM 2 exit block
 
Sunday July 30 2017
TimeRepliesSubject
6:55PM 1 lli -force-interpreter Error
3:47PM 1 exit block
9:31AM 1 opt instcombine pass crash on alias function
4:36AM 0 setting program counter on power8
4:25AM 1 A possible bug in the assembly parser for ARM
1:11AM 0 ELLCC 2017-07-29 released
 
Saturday July 29 2017
TimeRepliesSubject
11:59AM 1 [cfe-dev] [5.0.0 Release] Release Candidate 1 tagged
9:50AM 1 Compiling LLVM to LLVM IR
8:32AM 1 Compiling LLVM to LLVM IR
8:28AM 1 ISelDAGToDAG breaks node ordering
5:33AM 2 [RFC] Add IR level interprocedural outliner for code size.
4:58AM 2 [RFC] Add IR level interprocedural outliner for code size.
1:38AM 1 Storing "blockaddress(@function, %block)" in a global variable?
1:03AM 1 Storing "blockaddress(@function, %block)" in a global variable?
 
Friday July 28 2017
TimeRepliesSubject
10:13PM 1 Tail merging "undef" with a defined register: wrong code
9:36PM 2 Test Error Paths for Expected & ErrorOr
9:17PM 1 Tail merging "undef" with a defined register: wrong code
9:00PM 1 Tail merging "undef" with a defined register: wrong code
7:18PM 1 Tail merging "undef" with a defined register: wrong code
6:59PM 1 Tail merging "undef" with a defined register: wrong code
6:08PM 1 Tail merging "undef" with a defined register: wrong code
3:36PM 0 AttributeError: 'str' object has no attribute 'type'
3:21PM 2 Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register
3:08PM 1 arbitrary bit number
12:58PM 1 arbitrary bit number
11:30AM 1 Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register
11:16AM 1 [5.0.0 Release] Release Candidate 1 tagged
10:32AM 1 arbitrary bit number
6:43AM 1 [Release-testers] [5.0.0 Release] Release Candidate 1 tagged
6:38AM 1 Purpose of various register classes in X86 target
5:47AM 2 Purpose of various register classes in X86 target
2:45AM 2 GEP with a null pointer base
12:17AM 2 [Release-testers] [5.0.0 Release] Release Candidate 1 tagged
 
Thursday July 27 2017
TimeRepliesSubject
10:43PM 1 Purpose of various register classes in X86 target
10:07PM 0 Buildmaster restart
7:20PM 1 Tail merging "undef" with a defined register: wrong code
6:52PM 1 Tail merging "undef" with a defined register: wrong code
6:47PM 1 Tail merging "undef" with a defined register: wrong code
6:40PM 1 Tail merging "undef" with a defined register: wrong code
5:03PM 0 llvm: How to get the call graph for a module of external node
4:42PM 1 setting program counter on power8
3:56PM 1 Test Error Paths for Expected & ErrorOr
3:54PM 1 Test Error Paths for Expected & ErrorOr
2:46PM 1 Test Error Paths for Expected & ErrorOr
2:07PM 1 Are there some strong naming conventions in TableGen?
2:06PM 1 llvm 5.0 release rc1 : ExecutionEngine fatal error on MCJIT::getFunctionAddress
2:01PM 0 Comparing constant values of aggregate types for equality
1:38PM 1 llvm 5.0 release rc1 : ExecutionEngine fatal error on MCJIT::getFunctionAddress
12:22PM 1 Are there some strong naming conventions in TableGen?
12:09PM 1 Test Error Paths for Expected & ErrorOr
9:54AM 1 Purpose of various register classes in X86 target
9:42AM 0 I can't exec BrainF to JIT my code !!!
7:18AM 1 Maintaining TBAA information in stack coloring pass
5:02AM 2 GEP with a null pointer base
4:12AM 0 GEP with a null pointer base
3:40AM 1 GEP with a null pointer base
 
Wednesday July 26 2017
TimeRepliesSubject
10:41PM 11 [5.0.0 Release] Release Candidate 1 tagged
9:36PM 1 armv7 pc-rel bx thumb instruction
8:56PM 1 armv7 pc-rel bx thumb instruction
8:52PM 1 [RFC] Add IR level interprocedural outliner for code size.
8:41PM 1 [RFC] Add IR level interprocedural outliner for code size.
7:54PM 1 [RFC] Add IR level interprocedural outliner for code size.
7:25PM 1 armv7 pc-rel bx thumb instruction
7:07PM 2 [RFC] Add IR level interprocedural outliner for code size.
6:24PM 2 Adding new fields to bugzilla
6:10PM 1 Adding new fields to bugzilla
5:52PM 1 armv7 pc-rel bx thumb instruction
5:10PM 1 [RFC] Add IR level interprocedural outliner for code size.
5:05PM 1 isSSA computation in MIR parser
4:52PM 1 Adding new fields to bugzilla
4:36PM 1 [RFC] Add IR level interprocedural outliner for code size.
4:31PM 1 [RFC] Add IR level interprocedural outliner for code size.
11:50AM 1 isSSA computation in MIR parser
11:44AM 1 loop canonical variables
11:34AM 1 [Patch] 64-bit Mach-O Universal getters.
11:33AM 0 'unsupported call to function' with user-defined functions
9:07AM 0 Optimization levels in llvm
7:24AM 1 loop canonical variables
5:36AM 3 [RFC] Add IR level interprocedural outliner for code size.
4:35AM 0 Moving stacks in LLVM
1:26AM 1 [RFC] Add IR level interprocedural outliner for code size.
 
Tuesday July 25 2017
TimeRepliesSubject
9:48PM 1 loop canonical variables
8:42PM 1 code duplication in cmake for sanitizer tests
8:21PM 2 Are SCEV normal form?
6:56PM 1 Where does the LLVM implement the Ubsan's instrumentations?
6:42PM 1 loop canonical variables
5:32PM 1 loop canonical variables
5:11PM 1 loop canonical variables
5:07PM 1 PGO, zlib and 'default.profraw'
4:59PM 2 [RFC] Add IR level interprocedural outliner for code size.
4:32PM 1 PGO, zlib and 'default.profraw'
4:31PM 2 [RFC] Add IR level interprocedural outliner for code size.
4:26PM 1 why is llvm.stacksave() necessary?
4:24PM 2 [RFC] Add IR level interprocedural outliner for code size.
4:13PM 1 llvmlite for tmp
4:12PM 1 loop canonical variables
3:46PM 1 why is llvm.stacksave() necessary?
3:40PM 1 why is llvm.stacksave() necessary?
2:32PM 1 [Debug] Elide the unconditional branch instructions
2:30PM 1 How to migrate x86_sse2_psrl_dq after LLVM v3.8?
1:49PM 1 Identify c-style pointer to array
12:29PM 1 undef value
12:15PM 1 undef value
11:35AM 1 undef value
11:27AM 1 why is llvm.stacksave() necessary?
11:17AM 1 why is llvm.stacksave() necessary?
9:48AM 1 HUGE constant expression generation
9:13AM 1 why is llvm.stacksave() necessary?
9:04AM 1 why is llvm.stacksave() necessary?
8:29AM 1 How to migrate x86_sse2_psrl_dq after LLVM v3.8?
8:04AM 1 PGO, zlib and 'default.profraw'
7:12AM 0 GEP with a null pointer base
6:28AM 1 Identify c-style pointer to array
5:25AM 1 [RFC] Add IR level interprocedural outliner for code size.
4:25AM 1 [RFC] Add IR level interprocedural outliner for code size.
4:17AM 1 [RFC] Add IR level interprocedural outliner for code size.
4:02AM 2 [RFC] Add IR level interprocedural outliner for code size.
3:31AM 2 [RFC] Add IR level interprocedural outliner for code size.
3:17AM 1 [Debug] Elide the unconditional branch instructions
1:38AM 1 Unreachable reviews.llvm.org
1:24AM 2 [RFC] Add IR level interprocedural outliner for code size.
1:05AM 0 LLVM Compiler Help Wanted: Polychain Capital Blockchain Infrastructure Project
 
Monday July 24 2017
TimeRepliesSubject
11:56PM 1 [RFC] Add IR level interprocedural outliner for code size.
11:36PM 1 [RFC] Add IR level interprocedural outliner for code size.
11:14PM 3 [RFC] Add IR level interprocedural outliner for code size.
11:09PM 1 [RFC] Add IR level interprocedural outliner for code size.
10:28PM 0 [RFC] Add IR level interprocedural outliner for code size.
10:08PM 1 LazyValueInfo vs ScalarEvolution
9:59PM 1 LazyValueInfo vs ScalarEvolution
9:43PM 1 LazyValueInfo vs ScalarEvolution
9:36PM 1 [RFC] Add IR level interprocedural outliner for code size.
9:29PM 1 LazyValueInfo vs ScalarEvolution
9:16PM 1 LazyValueInfo vs ScalarEvolution
9:00PM 1 Making an analysis availble during call lowering
8:59PM 2 [RFC] Add IR level interprocedural outliner for code size.
8:52PM 1 Making an analysis availble during call lowering
8:44PM 1 LazyValueInfo vs ScalarEvolution
8:42PM 2 [RFC] Add IR level interprocedural outliner for code size.
8:34PM 1 LazyValueInfo vs ScalarEvolution
7:30PM 1 Adding new fields to bugzilla
6:55PM 2 [RFC] Add IR level interprocedural outliner for code size.
6:12PM 1 [RFC] Add IR level interprocedural outliner for code size.
6:05PM 0 RFC: A new llvm-dlltool driver and llvm-lib driver improvements
5:36PM 0 LLVM Weekly - #186, Jul 24th 2017
4:35PM 1 [X86] Memory folding tables in x86 backend
4:08PM 2 GEP with a null pointer base
3:38PM 1 Advise on which copy to use.
2:11PM 1 LLVM coverage report
2:05PM 1 How to lower a 'Store' node using the list<dag> pattern.
12:38PM 1 [RFC] Add IR level interprocedural outliner for code size.
10:34AM 1 How to lower a 'Store' node using the list<dag> pattern.
5:32AM 1 Is there any pass existing in llvm which does machine copy propogation ?
4:50AM 0 How to migrate Target option PositionIndependentExecutable for LLVM v3.9?
 
Sunday July 23 2017
TimeRepliesSubject
9:06PM 1 Advise on which copy to use.
6:32PM 1 [RFC] Add IR level interprocedural outliner for code size.
2:09PM 1 [X86] Memory folding tables in x86 backend
11:19AM 1 [X86] Memory folding tables in x86 backend
10:31AM 1 setOperationAction(ISD::ADD, MVT::v16i32, Legal) in isellowering.cpp
8:48AM 1 [X86] Memory folding tables in x86 backend
7:43AM 1 [RFC] Add IR level interprocedural outliner for code size.
3:14AM 0 LLVM as a native assembly instrumentation tool
1:45AM 1 Can someone take a quick look at this?
1:23AM 2 [RFC] dereferenceable metadata
 
Saturday July 22 2017
TimeRepliesSubject
11:05PM 2 [RFC] Add IR level interprocedural outliner for code size.
10:23PM 1 [RFC] Add IR level interprocedural outliner for code size.
5:33PM 1 [GreenDragon] Jenkins Plugin and Core maintenance
1:06PM 1 Where does the LLVM implement the Ubsan's instrumentations?
5:55AM 2 GEP with a null pointer base
5:03AM 2 GEP with a null pointer base
1:29AM 2 GEP with a null pointer base
12:00AM 3 GEP with a null pointer base
 
Friday July 21 2017
TimeRepliesSubject
8:45PM 1 Will libFuzzer be part of future release binary packages?
8:38PM 1 Will libFuzzer be part of future release binary packages?
8:30PM 1 Will libFuzzer be part of future release binary packages?
7:56PM 0 New buildbot admin
7:47PM 1 Issue with DAG legalization of brcond, setcc, xor
7:40PM 2 Issue with DAG legalization of brcond, setcc, xor
7:20PM 0 LLVM Social Berlin #9
7:05PM 0 [llvm] r303387 - [InstCombine] add more tests for xor-of-icmps; NFC
7:02PM 1 Which assumptions do llvm.memcpy/memmove/memset.* make when the count is 0?
6:39PM 2 Which assumptions do llvm.memcpy/memmove/memset.* make when the count is 0?
6:39PM 0 gcc's POINTER_PLUS_EXPR REG_POINTER
6:13PM 2 Issue with DAG legalization of brcond, setcc, xor
6:00PM 1 Issue with DAG legalization of brcond, setcc, xor
5:22PM 1 Where does the LLVM implement the Ubsan's instrumentations?
5:17PM 1 Adding Flag Support in LLVM Backend
5:01PM 1 [RFC] Add IR level interprocedural outliner for code size.
4:58PM 1 A bug related with undef value when bootstrap MemorySSA.cpp
3:31PM 2 Which assumptions do llvm.memcpy/memmove/memset.* make when the count is 0?
3:28PM 1 [SPIR/PTX] Divergence analysis for BasicBlocks
3:21PM 1 [SPIR/PTX] Divergence analysis for BasicBlocks
3:13PM 1 [SPIR/PTX] Divergence analysis for BasicBlocks
3:03PM 1 type information about instruction
2:52PM 1 type information about instruction
2:35PM 1 type information about instruction
2:25PM 1 Is there any pass existing in llvm which does machine copy propogation ?
1:04PM 2 Where does the LLVM implement the Ubsan's instrumentations?
11:49AM 1 type information about instruction
9:33AM 1 Adding Flag Support in LLVM Backend
9:24AM 1 [RFC] Add IR level interprocedural outliner for code size.
8:47AM 1 Adding Flag Support in LLVM Backend
7:18AM 1 Is there any pass existing in llvm which does machine copy propogation ?
6:48AM 1 Identify a new type
6:27AM 1 Which assumptions do llvm.memcpy/memmove/memset.* make when the count is 0?
4:06AM 1 Which assumptions do llvm.memcpy/memmove/memset.* make when the count is 0?
4:00AM 1 Which assumptions do llvm.memcpy/memmove/memset.* make when the count is 0?
3:46AM 1 Which assumptions do llvm.memcpy/memmove/memset.* make when the count is 0?
3:41AM 1 Where does the LLVM implement the Ubsan's instrumentations?
1:55AM 1 Where does the LLVM implement the Ubsan's instrumentations?
1:46AM 1 Where does the LLVM implement the Ubsan's instrumentations?
 
Thursday July 20 2017
TimeRepliesSubject
11:07PM 2 FYI: Ninja-build user may use CMake-3.9
10:47PM 4 [RFC] Add IR level interprocedural outliner for code size.
9:35PM 1 Which assumptions do llvm.memcpy/memmove/memset.* make when the count is 0?
7:10PM 0 FYI: Ninja-build user may use CMake-3.9
6:22PM 2 GEP with a null pointer base
5:18PM 2 status of DebugInfo/PDB/Native
5:12PM 1 status of DebugInfo/PDB/Native
4:52PM 0 Identifying MachineOperands that are part of an address specification
4:49PM 1 Value
4:16PM 2 FYI: Ninja-build user may use CMake-3.9
4:04PM 1 [5.0.0 Release] The release branch is open; trunk is now 6.0.0
3:31PM 1 FYI: Ninja-build user may use CMake-3.9
3:05PM 1 Value
2:56PM 1 Value
2:43PM 1 Value
2:21PM 1 Creating int8** Pointer - Debug build works but not Release
2:07PM 0 [cfe-dev] Issue compiling x86 assembly code with clang
2:02PM 2 Value
1:32PM 1 Value
1:21PM 1 Value
1:21PM 0 (no subject)
12:58PM 1 [RFC] dereferenceable metadata
12:49PM 1 error:Ran out of lanemask bits to represent subregisterr
9:24AM 2 Issue compiling x86 assembly code with clang
8:16AM 1 error:Ran out of lanemask bits to represent subregisterr
6:27AM 1 error:Ran out of lanemask bits to represent subregisterr
2:28AM 2 Issue with DAG legalization of brcond, setcc, xor
1:07AM 1 [RFC] dereferenceable metadata
 
Wednesday July 19 2017
TimeRepliesSubject
10:08PM 2 error:Ran out of lanemask bits to represent subregisterr
10:04PM 2 error:Ran out of lanemask bits to represent subregisterr
10:02PM 1 error:Ran out of lanemask bits to represent subregisterr
9:47PM 1 LNT on pypy and documentation build
9:36PM 3 error:Ran out of lanemask bits to represent subregisterr
9:30PM 1 error:Ran out of lanemask bits to represent subregisterr
9:26PM 1 error:Ran out of lanemask bits to represent subregisterr
9:18PM 1 error:Ran out of lanemask bits to represent subregisterr
9:08PM 2 GlobalISel legalization guarantees
8:36PM 1 error:Ran out of lanemask bits to represent subregisterr
8:25PM 1 error:Ran out of lanemask bits to represent subregisterr
8:19PM 1 Is clang+llvm deterministisc?
8:03PM 1 error:Ran out of lanemask bits to represent subregisterr
7:56PM 1 error:Ran out of lanemask bits to represent subregisterr
7:53PM 1 [RFC] dereferenceable metadata
7:20PM 0 New buildbot admin
7:08PM 1 error:Ran out of lanemask bits to represent subregisterr
6:38PM 1 error:Ran out of lanemask bits to represent subregisterr
4:55PM 0 LLVM buildmaster will be updated and restarted tonight
3:58PM 1 [RFC][ThinLTO] llvm-dis ThinLTO summary dump format
3:54PM 2 [5.0.0 Release] The release branch is open; trunk is now 6.0.0
3:52PM 1 [RFC][ThinLTO] llvm-dis ThinLTO summary dump format
3:47PM 1 [RFC][ThinLTO] llvm-dis ThinLTO summary dump format
3:43PM 1 [RFC][ThinLTO] llvm-dis ThinLTO summary dump format
3:31PM 2 [RFC][ThinLTO] llvm-dis ThinLTO summary dump format
2:55PM 1 PGO, zlib and 'default.profraw'
1:19PM 1 GEP with a null pointer base
12:57PM 1 error:Ran out of lanemask bits to represent subregisterr
12:10PM 0 Failing unit tests
8:51AM 1 error:Ran out of lanemask bits to represent subregisterr
12:21AM 1 A bug related with undef value when bootstrap MemorySSA.cpp
 
Tuesday July 18 2017
TimeRepliesSubject
11:15PM 1 A bug related with undef value when bootstrap MemorySSA.cpp
11:03PM 1 A bug related with undef value when bootstrap MemorySSA.cpp
10:40PM 2 A bug related with undef value when bootstrap MemorySSA.cpp
9:40PM 1 PGO, zlib and 'default.profraw'
8:04PM 1 PGO, zlib and 'default.profraw'
6:50PM 1 LNT on pypy and documentation build
6:49PM 1 Next steps for optimization remarks?
6:39PM 1 PGO, zlib and 'default.profraw'
6:37PM 2 PGO, zlib and 'default.profraw'
6:36PM 1 [RFC] dereferenceable metadata
6:24PM 1 LNT on pypy and documentation build
6:21PM 1 LNT on pypy and documentation build
6:06PM 1 LNT on pypy and documentation build
5:48PM 1 LNT on pypy and documentation build
4:53PM 1 PGO, zlib and 'default.profraw'
3:41PM 1 Question
2:05PM 2 PGO, zlib and 'default.profraw'
1:38PM 1 get ty2
10:58AM 0 error:Ran out of lanemask bits to represent subregister
10:09AM 1 get ty2
4:00AM 0 linker warning while using PluginLoader with PassInfo
3:18AM 1 [SPIR-V] SPIR-V in LLVM
12:33AM 1 [RFC][ThinLTO] llvm-dis ThinLTO summary dump format
12:18AM 2 [RFC][ThinLTO] llvm-dis ThinLTO summary dump format
12:11AM 2 A bug related with undef value when bootstrap MemorySSA.cpp
 
Monday July 17 2017
TimeRepliesSubject
11:49PM 1 [RFC][ThinLTO] llvm-dis ThinLTO summary dump format
9:32PM 0 [compiler_rt] buildgo.sh warnings
9:23PM 1 moving libfuzzer to compiler-rt?
9:20PM 1 moving libfuzzer to compiler-rt?
9:18PM 1 moving libfuzzer to compiler-rt?
9:09PM 1 A bug related with undef value when bootstrap MemorySSA.cpp
9:06PM 1 moving libfuzzer to compiler-rt?
8:56PM 2 A bug related with undef value when bootstrap MemorySSA.cpp
8:53PM 1 A bug related with undef value when bootstrap MemorySSA.cpp
8:37PM 1 A bug related with undef value when bootstrap MemorySSA.cpp
8:34PM 1 A bug related with undef value when bootstrap MemorySSA.cpp
6:43PM 1 A bug related with undef value when bootstrap MemorySSA.cpp
6:24PM 2 An update on the DominatorTree and incremental dominators
6:21PM 2 A bug related with undef value when bootstrap MemorySSA.cpp
6:18PM 0 LLVM Weekly - #185, Jul 17th 2017
6:18PM 1 A bug related with undef value when bootstrap MemorySSA.cpp
6:14PM 1 [LLD] Linker Relaxation
5:32PM 1 A bug related with undef value when bootstrap MemorySSA.cpp
5:26PM 1 [SPIR-V] SPIR-V in LLVM
5:01PM 1 A bug related with undef value when bootstrap MemorySSA.cpp
3:35PM 1 questions about backport to 3.8/3.9/4.0
1:55PM 3 [SPIR-V] SPIR-V in LLVM
1:11PM 2 [RFC][ThinLTO] llvm-dis ThinLTO summary dump format
10:09AM 1 Guidance on Debugging LLVM error
10:07AM 1 Guidance on Debugging LLVM error
9:04AM 1 value range propagation
8:38AM 1 PartialAlias: different start addresses
8:24AM 1 A bug related with undef value when bootstrap MemorySSA.cpp
8:09AM 1 value range propagation
7:36AM 1 Is clang+llvm deterministisc?
 
Sunday July 16 2017
TimeRepliesSubject
10:46PM 1 PartialAlias: different start addresses
9:58PM 1 PartialAlias: different start addresses
9:34PM 1 PartialAlias: different start addresses
8:35PM 1 PartialAlias: different start addresses
8:27PM 2 PartialAlias: different start addresses
7:49PM 2 Is clang+llvm deterministisc?
7:45PM 1 PartialAlias: different start addresses
1:28PM 1 [Module TS] Help
3:22AM 2 Is clang+llvm deterministisc?
1:46AM 1 A bug related with undef value when bootstrap MemorySSA.cpp
12:11AM 1 A bug related with undef value when bootstrap MemorySSA.cpp
 
Saturday July 15 2017
TimeRepliesSubject
8:20PM 1 failing to optimize boolean ops on cmps
8:09PM 1 failing to optimize boolean ops on cmps
7:26PM 1 failing to optimize boolean ops on cmps
6:05PM 0 Linking CUDA bitcode files and generating CUDA executable
4:01PM 0 [Job Ad] Compiler engineering positions at Julia Computing
2:01PM 1 PartialAlias: different start addresses
12:58PM 1 SectionMemoryManager::finalizeMemory ... read only data become executable?
12:55PM 1 SectionMemoryManager::finalizeMemory ... read only data become executable?
12:35PM 1 PartialAlias: different start addresses
11:57AM 1 SectionMemoryManager::finalizeMemory ... read only data become executable?
9:51AM 1 PartialAlias: different start addresses
8:13AM 1 apt.llvm.org: Ubuntu Trusty update rate
7:36AM 0 Help request: Output reshuffling
5:37AM 0 Unexpected performance issue in `findAnalysisPass`
12:23AM 0 buildbot failure in Quic Tools Production Bot on arm-clang-50
 
Friday July 14 2017
TimeRepliesSubject
10:40PM 1 A Prototype to Track Input Read for Sparse File Fuzzing
10:38PM 1 questions about backport to 3.8/3.9/4.0
10:18PM 1 SectionMemoryManager::finalizeMemory ... read only data become executable?
9:47PM 1 PartialAlias: different start addresses
9:46PM 1 SectionMemoryManager::finalizeMemory ... read only data become executable?
9:37PM 1 PartialAlias: different start addresses
9:27PM 1 questions about backport to 3.8/3.9/4.0
9:03PM 1 failing to optimize boolean ops on cmps
8:25PM 1 PartialAlias: different start addresses
8:06PM 1 PartialAlias: different start addresses
8:00PM 1 PartialAlias: different start addresses
7:50PM 1 PartialAlias: different start addresses
7:04PM 1 failing to optimize boolean ops on cmps
6:54PM 1 failing to optimize boolean ops on cmps
6:46PM 3 failing to optimize boolean ops on cmps
6:38PM 2 failing to optimize boolean ops on cmps
6:32PM 1 error:Ran out of lanemask bits to represent subregister
6:22PM 1 failing to optimize boolean ops on cmps
5:52PM 1 [SPIR/PTX] Divergence analysis for BasicBlocks
5:52PM 1 Next steps for optimization remarks?
5:44PM 2 failing to optimize boolean ops on cmps
5:39PM 0 questions about backport to 3.8/3.9/4.0
5:36PM 1 questions about backport to 3.8/3.9/4.0
5:36PM 1 error:Ran out of lanemask bits to represent subregister
5:29PM 1 error:Ran out of lanemask bits to represent subregister
5:23PM 1 error:Ran out of lanemask bits to represent subregister
5:22PM 2 Next steps for optimization remarks?
5:16PM 1 error:Ran out of lanemask bits to represent subregister
5:15PM 1 Marking memory as immutable in LLVM IR
5:09PM 1 error:Ran out of lanemask bits to represent subregister
5:07PM 1 error:Ran out of lanemask bits to represent subregister
4:54PM 1 failing to optimize boolean ops on cmps
4:17PM 1 apt.llvm.org: Ubuntu Trusty update rate
4:10PM 3 SectionMemoryManager::finalizeMemory ... read only data become executable?
3:45PM 1 failing to optimize boolean ops on cmps
3:33PM 1 error:Ran out of lanemask bits to represent subregister
3:27PM 1 failing to optimize boolean ops on cmps
3:21PM 4 Next steps for optimization remarks?
12:22PM 0 LoopSimplify pass prevents loop unrolling
10:50AM 1 error:Ran out of lanemask bits to represent subregister
10:19AM 1 Building aggregate types with dynamically sized elements
10:03AM 1 Building aggregate types with dynamically sized elements
9:58AM 1 Problems generating Mach-O File (x86_64 , osx 10.12)
9:57AM 0 Strange assertion error in RegisterCoalescer.cpp - "Missing recursion" - related to bundles needed for predicated blocks
9:55AM 1 Building aggregate types with dynamically sized elements
9:25AM 1 No email notifications from Phabricator
8:26AM 1 Building aggregate types with dynamically sized elements
8:12AM 1 No email notifications from Phabricator
8:12AM 1 Building aggregate types with dynamically sized elements
7:47AM 1 No email notifications from Phabricator
1:18AM 1 failing to optimize boolean ops on cmps
 
Thursday July 13 2017
TimeRepliesSubject
11:40PM 1 failing to optimize boolean ops on cmps
11:37PM 1 failing to optimize boolean ops on cmps
11:10PM 1 failing to optimize boolean ops on cmps
10:08PM 1 How to add custom instrumentation?
9:15PM 1 GEP with a null pointer base
9:12PM 1 failing to optimize boolean ops on cmps
9:07PM 1 The undef story
9:04PM 1 A Prototype to Track Input Read for Sparse File Fuzzing
8:59PM 1 The undef story
8:45PM 1 How to add custom instrumentation?
8:43PM 2 LLVM (Cool/Warm) DOT Printers for Profiling
8:34PM 1 Question about thinLTO
6:27PM 1 ThinLTO and the C API
5:33PM 1 RFC: Harvard architectures and default address spaces
5:25PM 1 RFC: Harvard architectures and default address spaces
4:38PM 1 Question about thinLTO
4:30PM 2 Swallowing of input in FileCheck
3:45PM 1 Question about thinLTO
3:37PM 1 Question about thinLTO
2:19PM 1 Question about thinLTO
2:00PM 1 RFC: Harvard architectures and default address spaces
11:02AM 2 Deprecating the experimental microMIPS64R6 backend
10:55AM 2 *** GMX Spamverdacht *** Re: clang 4.0.0: Invalid code for builtin floating point function with -mfloat-abi=hard -ffast-math (ARM)
10:38AM 1 RFC: Harvard architectures and default address spaces
10:21AM 1 Deprecating the experimental microMIPS64R6 backend
10:14AM 1 Deprecating the experimental microMIPS64R6 backend
10:07AM 1 *** GMX Spamverdacht *** Re: clang 4.0.0: Invalid code for builtin floating point function with -mfloat-abi=hard -ffast-math (ARM)
9:54AM 1 Question about thinLTO
9:18AM 0 How to add custom instrumentation?
8:57AM 1 How to add custom instrumentation?
8:25AM 0 [ORC] Compile On Demand and static constructors
7:57AM 1 How to add custom instrumentation?
6:53AM 0 CallGraphNode giving incorrect function Name
6:42AM 0 The doubt to LLVM.org-How to add the new type?
2:57AM 2 [LLD] Linker Relaxation
 
Wednesday July 12 2017
TimeRepliesSubject
11:46PM 0 *** GMX Spamverdacht *** Re: clang 4.0.0: Invalid code for builtin floating point function with -mfloat-abi=hard -ffast-math (ARM)
11:36PM 1 [LLD] Adding WebAssembly support to lld
10:26PM 1 moving libfuzzer to compiler-rt?
10:23PM 1 [LLD] Adding WebAssembly support to lld
10:07PM 1 moving libfuzzer to compiler-rt?
10:07PM 2 [LLD] Linker Relaxation
9:55PM 1 ThinLTO and the C API
9:29PM 1 ThinLTO and the C API
9:18PM 1 moving libfuzzer to compiler-rt?
9:16PM 1 moving libfuzzer to compiler-rt?
9:11PM 1 moving libfuzzer to compiler-rt?
8:54PM 1 A Prototype to Track Input Read for Sparse File Fuzzing
8:27PM 1 moving libfuzzer to compiler-rt?
7:48PM 2 moving libfuzzer to compiler-rt?
7:41PM 2 moving libfuzzer to compiler-rt?
6:58PM 1 moving libfuzzer to compiler-rt?
6:54PM 1 moving libfuzzer to compiler-rt?
6:51PM 1 [RFC][GlobalISel] Making GlobalISel non-optional in the build
6:34PM 1 moving libfuzzer to compiler-rt?
6:34PM 1 [RFC][GlobalISel] Making GlobalISel non-optional in the build
6:33PM 1 moving libfuzzer to compiler-rt?
6:31PM 1 [LLD] Adding WebAssembly support to lld
6:30PM 2 moving libfuzzer to compiler-rt?
6:17PM 2 GEP with a null pointer base
6:07PM 2 [LLD] Linker Relaxation
6:01PM 2 moving libfuzzer to compiler-rt?
5:25PM 1 Question about thinLTO
5:19PM 1 Question about thinLTO
4:56PM 1 Question about thinLTO
4:51PM 1 [ThinLTO] Making ThinLTO functions not fail hasExactDefinition (specifically preventing it from being derefined)
4:45PM 1 A strange problem about type i64 for LLVM
4:24PM 1 A strange problem about type i64 for LLVM
3:26PM 1 RFC: Harvard architectures and default address spaces
3:16PM 1 A strange problem about type i64 for LLVM
3:10PM 1 A strange problem about type i64 for LLVM
11:10AM 1 [LLD] Linker Relaxation
9:37AM 0 Compiler and Code Generation Social Zurich - July 13th
9:24AM 1 GEP with a null pointer base
9:23AM 1 noopt
7:26AM 2 [LLD] Linker Relaxation
7:18AM 1 [cfe-dev] FYI: ENABLE_MODULES would make building faster
7:05AM 0 [5.0.0 Release] One week to the branch
6:08AM 1 Using new types v32f32, v32f64 in llvm backend not possible
5:57AM 2 Call for Talks, Tutorials, BoFs, Panels, Student Research Competition, and More!
5:04AM 1 Using new types v32f32, v32f64 in llvm backend not possible
2:02AM 1 moving libfuzzer to compiler-rt?
2:00AM 1 libfuzzer tests on Linux
 
Tuesday July 11 2017
TimeRepliesSubject
11:30PM 0 LLVM buildmaster will be updated and restarted tonight
10:18PM 1 RFC: Harvard architectures and default address spaces
9:54PM 1 [ThinLTO] Making ThinLTO functions not fail hasExactDefinition (specifically preventing it from being derefined)
9:21PM 2 [cfe-dev] FYI: ENABLE_MODULES would make building faster
9:08PM 3 [IR canonicalization] 6 ways to choose {-1,0,1}
9:00PM 1 [IR canonicalization] 6 ways to choose {-1,0,1}
8:20PM 0 Why llvm emits the fixup referring to nop or nop-like instruction?
7:56PM 1 Using new types v32f32, v32f64 in llvm backend not possible
7:49PM 1 Using new types v32f32, v32f64 in llvm backend not possible
7:37PM 1 [LLD] Linker Relaxation
7:27PM 1 [ThinLTO] Making ThinLTO functions not fail hasExactDefinition (specifically preventing it from being derefined)
6:49PM 1 intrinsics
6:38PM 1 intrinsics
6:33PM 1 intrinsics
6:27PM 2 [LLD] Linker Relaxation
6:21PM 3 [LLD] Linker Relaxation
6:19PM 1 intrinsics
6:16PM 1 intrinsics
5:41PM 1 [LLD] Linker Relaxation
5:26PM 1 intrinsics
4:49PM 1 error: In anonymous_4820: Unrecognized node 'VRR128'!
4:14PM 1 error: In anonymous_4820: Unrecognized node 'VRR128'!
4:00PM 1 error: In anonymous_4820: Unrecognized node 'VRR128'!
3:55PM 1 error: In anonymous_4820: Unrecognized node 'VRR128'!
2:55PM 1 error: In anonymous_4820: Unrecognized node 'VRR128'!
2:27PM 1 error: In anonymous_4820: Unrecognized node 'VRR128'!
2:00PM 1 Using TSAN along with custom llvm IR pass
1:40PM 1 [LLD] Linker Relaxation
1:39PM 1 RFC: Harvard architectures and default address spaces
1:26PM 1 Using TSAN along with custom llvm IR pass
1:20PM 1 Using new types v32f32, v32f64 in llvm backend not possible
1:13PM 1 RFC: Harvard architectures and default address spaces
1:02PM 1 Zero-extending function parameters on x86_64
12:40PM 1 Invalid link on Github
12:31PM 1 returning Expected<tool_output_file>
12:14PM 3 [LLD] Linker Relaxation
10:59AM 1 [LLD] Linker Relaxation
10:09AM 1 [LLD] Linker Relaxation
9:03AM 0 Custom MCTargetAsmParser for a target
8:22AM 1 Using new types v32f32, v32f64 in llvm backend not possible
5:54AM 4 RFC: Harvard architectures and default address spaces
4:00AM 0 Conditional Register Assignment based on the no of loop iterations
2:13AM 1 Problems with registering of ModulePass (with Dependencies)
 
Monday July 10 2017
TimeRepliesSubject
11:13PM 1 [LLD] Adding WebAssembly support to lld
9:20PM 1 Problems with registering of ModulePass (with Dependencies)
8:01PM 1 Loop branching inefficiencies in Backend output
6:42PM 1 GEP with a null pointer base
6:36PM 2 GEP with a null pointer base
5:29PM 0 LLVM Weekly - #184, Jul 10th 2017
5:13PM 1 [IR canonicalization] 6 ways to choose {-1,0,1}
4:37PM 1 disable optimizarions
4:32PM 1 disable optimizarions
4:04PM 1 Swallowing of input in FileCheck
3:55PM 1 "no-jump-table": Attribute vs flag
3:55PM 1 [ThinLTO] Making ThinLTO functions not fail hasExactDefinition (specifically preventing it from being derefined)
3:36PM 1 Problems generating Mach-O File (x86_64 , osx 10.12)
3:33PM 1 [IR canonicalization] 6 ways to choose {-1,0,1}
2:57PM 1 Problems with registering of ModulePass (with Dependencies)
1:26PM 1 Shipping LLVM.dll for the C API with the Windows installer.
1:20PM 1 Shipping LLVM.dll for the C API with the Windows installer.
1:00PM 1 Using TSAN along with custom llvm IR pass
11:18AM 1 LLVM 4.0 with clang 4.0
11:09AM 1 Using TSAN along with custom llvm IR pass
10:46AM 1 Conditional Register Assignment based on the no of loop iterations
9:44AM 2 FYI: ENABLE_MODULES would make building faster
5:28AM 1 [IR canonicalization] 6 ways to choose {-1,0,1}
5:22AM 1 Conditional Register Assignment based on the no of loop iterations
5:21AM 3 Using TSAN along with custom llvm IR pass
4:29AM 1 Conditional Register Assignment based on the no of loop iterations
4:17AM 1 Conditional Register Assignment based on the no of loop iterations
2:19AM 0 JITEmitDebugInfo in LLVM 4.0.1
1:23AM 1 GEP with a null pointer base
 
Sunday July 9 2017
TimeRepliesSubject
11:36PM 1 Loop branching inefficiencies in Backend output
11:07PM 1 Uncovering non-determinism in LLVM - The Next Steps
11:02PM 0 Question
10:57PM 1 Uncovering non-determinism in LLVM - The Next Steps
9:07PM 1 Dataflow analysis regression in 3.7
8:58PM 0 buildbot failure in LLVM on sanitizer-ppc64le-linux
8:53PM 1 Dataflow analysis regression in 3.7
8:10PM 1 GEP with a null pointer base
5:26PM 1 Uncovering non-determinism in LLVM - The Next Steps
5:24PM 1 Dataflow analysis regression in 3.7
4:19PM 1 Uncovering non-determinism in LLVM - The Next Steps
3:57PM 1 Dataflow analysis regression in 3.7
2:44PM 1 Invalid link on Github
1:50PM 1 Using TSAN along with custom llvm IR pass
7:07AM 1 Identification of LEA instructions with complex addressing mode
6:20AM 1 RFC: Identification of LEA instructions with complex addressing mode
2:33AM 1 GEP with a null pointer base
 
Saturday July 8 2017
TimeRepliesSubject
6:18PM 1 Swallowing of input in FileCheck
5:07PM 1 Swallowing of input in FileCheck
2:32PM 2 Swallowing of input in FileCheck
10:55AM 1 Invalid link on Github
7:37AM 1 Caller callee calling convention enforcement in C++ bin. code
7:27AM 1 Error in v64i32 type in x86 backend
6:46AM 1 Error in v64i32 type in x86 backend
6:23AM 1 Error in v64i32 type in x86 backend
6:03AM 2 Error in v64i32 type in x86 backend
6:00AM 0 Fwd: Error in v64i32 type in x86 backend
5:10AM 0 Error in v64i32 type in x86 backend
4:59AM 1 Error in v64i32 type in x86 backend
4:55AM 1 Error in v64i32 type in x86 backend
4:29AM 1 Error in v64i32 type in x86 backend
3:48AM 1 Error in v64i32 type in x86 backend
3:41AM 1 Error in v64i32 type in x86 backend
2:07AM 1 Invalid link on Github
12:22AM 0 LLVM buildmaster will be updated and restarted tonight
 
Friday July 7 2017
TimeRepliesSubject
11:24PM 1 Swallowing of input in FileCheck
10:44PM 3 GEP with a null pointer base
10:42PM 0 RFC: Cleaning up the Itanium demangler
10:40PM 1 Missing symbol `typeinfo for llvm::raw_ostream' in LLVM-4.0.so
10:05PM 1 Swallowing of input in FileCheck
9:32PM 1 Lowering Select to Two Predicated Movs
9:19PM 1 Swallowing of input in FileCheck
8:59PM 2 Dataflow analysis regression in 3.7
8:47PM 1 Dataflow analysis regression in 3.7
8:34PM 1 Lowering Select to Two Predicated Movs
8:20PM 1 Swallowing of input in FileCheck
7:37PM 1 Lowering Select to Two Predicated Movs
7:10PM 1 Lowering Select to Two Predicated Movs
6:57PM 1 CMake dependencies and building LLVM
6:20PM 1 Lowering Select to Two Predicated Movs
6:12PM 1 Lowering Select to Two Predicated Movs
5:41PM 1 CMake dependencies and building LLVM
5:16PM 2 Uncovering non-determinism in LLVM - The Next Steps
4:58PM 1 Uncovering non-determinism in LLVM - The Next Steps
4:16PM 1 m32 flag disables vectorization
4:12PM 1 CMake dependencies and building LLVM
4:01PM 1 Uncovering non-determinism in LLVM - The Next Steps
3:52PM 1 Dataflow analysis regression in 3.7
3:19PM 1 Invalid link on Github
2:07PM 1 Unhandled reg/opcode register encoding VR2048 Error in backend
1:46PM 1 CMake dependencies and building LLVM
12:33PM 1 Unhandled reg/opcode register encoding VR2048 Error in backend
10:35AM 1 Invalid link on Github
9:31AM 1 trunc nsw/nuw?
7:55AM 2 trunc nsw/nuw?
7:43AM 1 Linking bugpoint - memory usage
5:56AM 1 [RFC][SVE] Supporting Scalable Vector Architectures in LLVM IR (take 2)
5:51AM 1 Error in v64i32 type in x86 backend
5:19AM 1 Error in v64i32 type in x86 backend
5:03AM 1 Error in v64i32 type in x86 backend
3:21AM 1 Error in v64i32 type in x86 backend
3:19AM 1 Obtain the execution time of one specified library function, such as CUDA library function.
3:02AM 1 [RFC][SVE] Supporting Scalable Vector Architectures in LLVM IR (take 2)
3:00AM 1 Error in v64i32 type in x86 backend
2:11AM 1 Error in v64i32 type in x86 backend
1:51AM 1 Error in v64i32 type in x86 backend
12:46AM 1 trunc nsw/nuw?
 
Thursday July 6 2017
TimeRepliesSubject
11:50PM 1 [RFC][GlobalISel] Making GlobalISel non-optional in the build
11:36PM 0 [Release-testers] LLVM 4.0.1 -final has been tagged
10:53PM 2 [RFC][SVE] Supporting Scalable Vector Architectures in LLVM IR (take 2)
10:38PM 2 [LLD] Adding WebAssembly support to lld
10:13PM 1 [RFC][SVE] Supporting Scalable Vector Architectures in LLVM IR (take 2)
10:07PM 2 GEP with a null pointer base
10:03PM 1 [RFC][SVE] Supporting Scalable Vector Architectures in LLVM IR (take 2)
9:58PM 1 GEP with a null pointer base
9:49PM 1 GEP with a null pointer base
9:05PM 1 GEP with a null pointer base
8:46PM 2 LLVM's loop strength reduction module
8:29PM 1 Getting actual value of local variable
8:19PM 1 GEP with a null pointer base
8:08PM 2 Uncovering non-determinism in LLVM - The Next Steps
8:06PM 1 GEP with a null pointer base
8:04PM 1 [DWARFv5] Reading the .debug_str_offsets section
8:02PM 1 [RFC][SVE] Supporting Scalable Vector Architectures in LLVM IR (take 2)
8:00PM 1 GEP with a null pointer base
7:54PM 1 GEP with a null pointer base
7:34PM 1 Uncovering non-determinism in LLVM - The Next Steps
7:32PM 1 [DWARFv5] Reading the .debug_str_offsets section
7:28PM 1 GEP with a null pointer base
7:17PM 2 GEP with a null pointer base
7:09PM 1 [LLD] Adding WebAssembly support to lld
7:05PM 2 GEP with a null pointer base
6:59PM 1 [DWARFv5] Reading the .debug_str_offsets section
6:55PM 1 ErrorInfo::message() possibly broken in LLVM-4.0.1
6:53PM 1 ErrorInfo::message() possibly broken in LLVM-4.0.1
6:52PM 1 GEP with a null pointer base
6:16PM 1 Shipping LLVM.dll for the C API with the Windows installer.
6:06PM 2 GEP with a null pointer base
5:55PM 1 ErrorInfo::message() possibly broken in LLVM-4.0.1
5:20PM 1 Uncovering non-determinism in LLVM - The Next Steps
5:20PM 1 Uncovering non-determinism in LLVM - The Next Steps
5:18PM 1 Error in v64i32 type in x86 backend
5:10PM 1 Uncovering non-determinism in LLVM - The Next Steps
4:45PM 1 [DWARFv5] Reading the .debug_str_offsets section
4:32PM 1 Uncovering non-determinism in LLVM - The Next Steps
4:12PM 1 Uncovering non-determinism in LLVM - The Next Steps
4:02PM 1 Should we split llvm Support and ADT?
3:55PM 1 Dataflow analysis regression in 3.7
3:41PM 1 trunc nsw/nuw?
3:34PM 1 Uncovering non-determinism in LLVM - The Next Steps
3:02PM 2 Uncovering non-determinism in LLVM - The Next Steps
2:24PM 2 trunc nsw/nuw?
1:35PM 1 [DWARFv5] Reading the .debug_str_offsets section
10:35AM 1 The doubt to LLVM.org-How to add the new type?
10:11AM 1 (no subject)
10:07AM 1 (no subject)
8:56AM 0 Duplicate emails from Phabricator
6:56AM 2 Uncovering non-determinism in LLVM - The Next Steps
6:16AM 1 LLVM's loop strength reduction module
6:04AM 1 Should we split llvm Support and ADT?
5:00AM 1 Dataflow analysis regression in 3.7
4:23AM 1 LLVM's loop strength reduction module
3:53AM 1 Should we split llvm Support and ADT?
3:39AM 1 Should we split llvm Support and ADT?
3:14AM 0 Should we split llvm Support and ADT?
2:51AM 1 The doubt to LLVM.org-How to add the new type?
2:18AM 2 Should we split llvm Support and ADT?
2:14AM 0 Should we split llvm Support and ADT?
1:46AM 2 Should we split llvm Support and ADT?
1:29AM 0 MSP430 code generation from LLVM IR
1:26AM 0 Should we split llvm Support and ADT?
1:24AM 0 LLVM X86 AVX Backend
1:24AM 2 MSP430 code generation from LLVM IR
1:19AM 0 MSP430 code generation from LLVM IR
1:15AM 2 LLVM X86 AVX Backend
12:51AM 2 MSP430 code generation from LLVM IR
12:43AM 3 Should we split llvm Support and ADT?
12:35AM 0 MSP430 code generation from LLVM IR
12:07AM 0 Should we split llvm Support and ADT?
12:01AM 2 Should we split llvm Support and ADT?
 
Wednesday July 5 2017
TimeRepliesSubject
11:50PM 3 MSP430 code generation from LLVM IR
11:39PM 0 Performance metrics with LLVM
10:59PM 2 Dataflow analysis regression in 3.7
10:13PM 1 [DWARFv5] Reading the .debug_str_offsets section
9:30PM 1 trunc nsw/nuw?
9:09PM 2 Performance metrics with LLVM
8:34PM 1 [DWARFv5] Reading the .debug_str_offsets section
8:10PM 0 trunc nsw/nuw?
8:09PM 2 trunc nsw/nuw?
5:38PM 0 Should we split llvm Support and ADT?
5:36PM 0 llvm-profdata determinism
5:02PM 1 Ok with mismatch between dead-markings in BUNDLE and bundled instructions?
4:22PM 1 Caller callee calling convention enforcement in C++ bin. code
4:20PM 0 Performance metrics with LLVM
3:49PM 0 A new error handler for bad alloc fault situations in long running processes
3:48PM 2 Performance metrics with LLVM
3:27PM 2 [compiler-rt] Proposed changes to MemoryMappingLayout (sanitizer_procmaps)
3:20PM 1 Fixed point data type support
3:07PM 1 [RFC] Placing profile name data, and coverage data, outside of object files
3:06PM 1 opt passes
2:59PM 0 trunc nsw/nuw?
2:58PM 1 opt passes
2:49PM 0 opt passes
7:19AM 0 DFS traversal on CallGraph
4:47AM 0 lab.llvm.org buildbots down?
12:37AM 0 July LLVM bay-area social is this Thursday!
 
Tuesday July 4 2017
TimeRepliesSubject
9:11PM 1 [LLD] Adding WebAssembly support to lld
8:10PM 0 [LLD] Adding WebAssembly support to lld
2:11PM 1 Avoid generating COPY instructions with TwoAddressInstructionPass for a region of MachineInstr
10:53AM 1 Adding new fields to bugzilla
10:49AM 0 Definitive list of optimisations at each optimisation level
9:25AM 2 opt passes
9:02AM 0 Performance metrics with LLVM
8:53AM 0 SVN commit issue: "Error: Couldn't perform atomic initialization"
8:04AM 1 Emails to llvm-commits disappearing?
7:48AM 2 Performance metrics with LLVM
6:49AM 2 LLVM no getInt128 in IRBuilder?
6:41AM 4 trunc nsw/nuw?
6:29AM 0 [RFC] Placing profile name data, and coverage data, outside of object files
6:29AM 0 [RFC] Placing profile name data, and coverage data, outside of object files
6:27AM 1 Performance metrics with LLVM
3:41AM 1 An issue with new PM's requirements on call graph changes
 
Monday July 3 2017
TimeRepliesSubject
11:43PM 0 An issue with new PM's requirements on call graph changes
10:51PM 1 List of alias analyses available in LLVM, and how to use them from llc
10:11PM 1 libunwind build errors on aarch64 during LLVM/Clang installation
9:11PM 0 trunc nsw/nuw?
8:51PM 1 [GlobalISel] G_LOAD/G_STORE i64/f64 handling
8:28PM 0 [GlobalISel] G_LOAD/G_STORE i64/f64 handling
7:38PM 2 trunc nsw/nuw?
7:07PM 0 [RFC] Placing profile name data, and coverage data, outside of object files
6:19PM 0 [RFC] Placing profile name data, and coverage data, outside of object files
6:12PM 3 [LLD] Adding WebAssembly support to lld
4:15PM 0 LLVM Weekly - #183, Jul 3rd 2017
3:13PM 0 Could LLVMConfig.cmake export the LLVM_USE_CRT_* fields?
12:08PM 0 [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
11:13AM 0 Ok with mismatch between dead-markings in BUNDLE and bundled instructions?
11:09AM 0 [cfe-dev] Unable to Receive Emails from Phabricator
10:20AM 2 Unable to Receive Emails from Phabricator
9:42AM 0 Wide load/store optimization question
8:58AM 0 type traits bug in clang 4.0.0?
8:51AM 1 Building llvm with clang and lld on arm and the llvm arm backend relocation on position independent code
8:42AM 2 type traits bug in clang 4.0.0?
7:20AM 0 Error while accessing reviews.llvm.org
5:19AM 1 Jacobi 5 Point Stencil Code not Vectorizing
12:47AM 1 Error while accessing reviews.llvm.org
 
Sunday July 2 2017
TimeRepliesSubject
6:11PM 0 Error while accessing reviews.llvm.org
5:38PM 3 Error while accessing reviews.llvm.org
5:18PM 2 Error while accessing reviews.llvm.org
10:50AM 2 [GlobalISel] G_LOAD/G_STORE i64/f64 handling
9:21AM 0 Set Vector Width in Polly
8:47AM 1 Jacobi 5 Point Stencil Code not Vectorizing
8:28AM 0 Jacobi 5 Point Stencil Code not Vectorizing
 
Saturday July 1 2017
TimeRepliesSubject
10:33PM 2 Jacobi 5 Point Stencil Code not Vectorizing
10:11PM 0 Jacobi 5 Point Stencil Code not Vectorizing
9:07PM 0 musttail & alwaysinline interaction
8:56PM 0 CGP: Break use-def graph loops in optimizeMemoryInst
8:54PM 3 Jacobi 5 Point Stencil Code not Vectorizing
8:53PM 0 An issue with new PM's requirements on call graph changes
8:24PM 0 The undef story
7:21PM 0 [RFC] Placing profile name data, and coverage data, outside of object files
7:14PM 0 The undef story
6:45PM 4 [IR canonicalization] 6 ways to choose {-1,0,1}
6:31PM 0 "Beginner" keyword for LLVM Bugzilla?
5:32PM 0 [LLD] Adding WebAssembly support to lld
5:02PM 0 [LLD] Adding WebAssembly support to lld
4:27PM 1 loop induction variables at IR level
3:37PM 0 Installing selected subset of LLVM Tools with shared build
3:10PM 0 The undef story
1:54PM 0 loop induction variables at IR level
12:34PM 0 Building llvm with clang and lld on arm and the llvm arm backend relocation on position independent code
12:30PM 0 Jacobi 5 Point Stencil Code not Vectorizing
11:08AM 2 Jacobi 5 Point Stencil Code not Vectorizing
8:56AM 2 loop induction variables at IR level
6:29AM 0 LLC Segmentation Fault in Matrix Multiplication
6:12AM 2 LLC Segmentation Fault in Matrix Multiplication
5:51AM 1 LLC Segmentation Fault in Matrix Multiplication
5:47AM 1 LLC Segmentation Fault in Matrix Multiplication
5:39AM 1 [RFC] Placing profile name data, and coverage data, outside of object files
5:25AM 2 [RFC] Placing profile name data, and coverage data, outside of object files
5:20AM 2 LLVM docs links broken
5:04AM 7 [RFC] Placing profile name data, and coverage data, outside of object files
3:16AM 1 [RFC] Placing profile name data, and coverage data, outside of object files
2:10AM 2 [LLD] Adding WebAssembly support to lld
2:01AM 2 [cfe-dev] Just a quick heads up -- removing BBVectorize from LLVM (and Clang)
1:32AM 1 [cfe-dev] Just a quick heads up -- removing BBVectorize from LLVM (and Clang)
12:54AM 3 [RFC] Placing profile name data, and coverage data, outside of object files
12:19AM 3 [LLD] Adding WebAssembly support to lld
12:09AM 1 KNL Assembly Code for Matrix Multiplication
12:03AM 1 KNL Assembly Code for Matrix Multiplication