| Tuesday February 28 2017 |
| Time | Replies | Subject |
|---|
| 11:45PM |
0 |
Running the compiler-rt builtins unit tests |
| 11:22PM |
2 |
Running the compiler-rt builtins unit tests |
| 9:50PM |
0 |
Noisy benchmark results? |
| 9:47PM |
1 |
Fix link on ProjectsWithLLVM page |
| 9:37PM |
2 |
Using binary versions of release candidates... |
| 8:53PM |
1 |
Noisy benchmark results? |
| 8:51PM |
2 |
Noisy benchmark results? |
| 8:44PM |
0 |
Teaching lit to expand glob expressions |
| 8:10PM |
0 |
[lld] We call SymbolBody::getVA redundantly a lot... |
| 7:03PM |
0 |
Working on open projects in clang in the upcoming GSOC |
| 5:47PM |
0 |
[lld] We call SymbolBody::getVA redundantly a lot... |
| 2:57PM |
0 |
LLVM Pass - Backend Instrumentation |
| 1:27PM |
0 |
[Proposal][RFC] Epilog loop vectorization |
| 1:09PM |
3 |
[Proposal][RFC] Epilog loop vectorization |
| 12:25PM |
0 |
GSoC 2017 |
| 12:19PM |
4 |
[lld] We call SymbolBody::getVA redundantly a lot... |
| 11:22AM |
2 |
LLVM Pass - Backend Instrumentation |
| 11:22AM |
1 |
[Proposal][RFC] Epilog loop vectorization |
| 9:10AM |
0 |
[Proposal][RFC] Epilog loop vectorization |
| 6:05AM |
1 |
rL296252 Made large integer operation codegen significantly worse. |
| 5:19AM |
0 |
rL296252 Made large integer operation codegen significantly worse. |
| 5:14AM |
0 |
LLVM_TARGETS_TO_BUILD |
| 5:02AM |
2 |
rL296252 Made large integer operation codegen significantly worse. |
| 4:47AM |
0 |
rL296252 Made large integer operation codegen significantly worse. |
| 4:22AM |
3 |
LLVM_TARGETS_TO_BUILD |
| 4:00AM |
0 |
LLVM_TARGETS_TO_BUILD |
| 2:57AM |
3 |
LLVM_TARGETS_TO_BUILD |
| 12:12AM |
0 |
March LLVM bay-area social is this Thursday! |
| 12:01AM |
2 |
rL296252 Made large integer operation codegen significantly worse. |
| |
| Monday February 27 2017 |
| Time | Replies | Subject |
|---|
| 11:35PM |
0 |
[Proposal][RFC] Epilog loop vectorization |
| 11:00PM |
1 |
lli can't find vsprintf |
| 10:51PM |
1 |
Problems using Clang with LLD on embedded ARM |
| 10:19PM |
2 |
[Proposal][RFC] Epilog loop vectorization |
| 9:18PM |
0 |
lli can't find vsprintf |
| 8:44PM |
2 |
lli can't find vsprintf |
| 8:06PM |
1 |
[Proposal][RFC] Epilog loop vectorization |
| 8:04PM |
0 |
[Proposal][RFC] Epilog loop vectorization |
| 8:02PM |
0 |
[Proposal][RFC] Epilog loop vectorization |
| 8:01PM |
4 |
[Proposal][RFC] Epilog loop vectorization |
| 7:58PM |
0 |
[Proposal][RFC] Epilog loop vectorization |
| 7:47PM |
0 |
[Proposal][RFC] Epilog loop vectorization |
| 7:42PM |
0 |
Noisy benchmark results? |
| 7:29PM |
2 |
[Proposal][RFC] Epilog loop vectorization |
| 6:43PM |
1 |
[DebugInfo] [DWARFv5] .debug_abbrev contents for different implicit_const values |
| 6:41PM |
2 |
[Proposal][RFC] Epilog loop vectorization |
| 6:15PM |
0 |
[DebugInfo] [DWARFv5] .debug_abbrev contents for different implicit_const values |
| 6:11PM |
0 |
[Proposal][RFC] Epilog loop vectorization |
| 5:47PM |
5 |
[Proposal][RFC] Epilog loop vectorization |
| 5:39PM |
0 |
[Proposal][RFC] Epilog loop vectorization |
| 5:29PM |
2 |
[Proposal][RFC] Epilog loop vectorization |
| 3:52PM |
1 |
How can I get the opcode length of an IR instruction in LLVM? |
| 3:50PM |
0 |
How can I get the opcode length of an IR instruction in LLVM? |
| 3:27PM |
0 |
[Proposal][RFC] Epilog loop vectorization |
| 3:24PM |
3 |
How can I get the opcode length of an IR instruction in LLVM? |
| 12:29PM |
4 |
[Proposal][RFC] Epilog loop vectorization |
| 12:22PM |
0 |
LLVM Weekly - #165, Feb 27th 2017 |
| 11:35AM |
0 |
Compiling LLVM with locally built clang | Errors |
| 11:05AM |
1 |
Noisy benchmark results? |
| 10:53AM |
0 |
Noisy benchmark results? |
| 10:32AM |
3 |
Noisy benchmark results? |
| 10:22AM |
2 |
LLVM social in Sweden? |
| 9:36AM |
0 |
Noisy benchmark results? |
| 8:46AM |
8 |
Noisy benchmark results? |
| 8:34AM |
2 |
How to catch EXCEPTION_ACCESS_VIOLATION exceptions on win64 |
| 7:11AM |
2 |
Compiling LLVM with locally built clang | Errors |
| 7:07AM |
1 |
When AVR backend generates mulsu instruction ? |
| 6:43AM |
0 |
When AVR backend generates mulsu instruction ? |
| 6:40AM |
2 |
When AVR backend generates mulsu instruction ? |
| 5:43AM |
0 |
When AVR backend generates mulsu instruction ? |
| |
| Sunday February 26 2017 |
| Time | Replies | Subject |
|---|
| 11:08PM |
1 |
FAIL: Why does the output of "llc -march=cpp .." fail to compile with clang 3.8 |
| 10:49PM |
0 |
Problems using Clang with LLD on embedded ARM |
| 10:44PM |
0 |
(no subject) |
| 10:25PM |
3 |
Problems using Clang with LLD on embedded ARM |
| 8:34PM |
0 |
setting funclet operand bundles |
| 5:23PM |
0 |
[Proposal][RFC] Epilog loop vectorization |
| 1:06PM |
0 |
FAIL: Why does the output of "llc -march=cpp .." fail to compile with clang 3.8 |
| 11:53AM |
2 |
FAIL: Why does the output of "llc -march=cpp .." fail to compile with clang 3.8 |
| 11:41AM |
2 |
When AVR backend generates mulsu instruction ? |
| 11:10AM |
0 |
Problems using Clang with LLD on embedded ARM |
| 8:44AM |
0 |
[EuroLLVM] Program available! Hacker's Lab topics wanted! |
| 5:38AM |
5 |
Problems using Clang with LLD on embedded ARM |
| |
| Saturday February 25 2017 |
| Time | Replies | Subject |
|---|
| 8:06PM |
0 |
rL296252 Made large integer operation codegen significantly worse. |
| 6:04PM |
1 |
Building with MSVC broken by D30246 (Fix zip iterator interface) |
| 5:51PM |
2 |
rL296252 Made large integer operation codegen significantly worse. |
| 5:30PM |
0 |
lli can't find vsprintf |
| 3:42PM |
2 |
[DebugInfo] [DWARFv5] .debug_abbrev contents for different implicit_const values |
| 9:06AM |
2 |
Help understanding and lowering LLVM IDS conditional codes correctly |
| 12:56AM |
2 |
lli can't find vsprintf |
| |
| Friday February 24 2017 |
| Time | Replies | Subject |
|---|
| 10:10PM |
0 |
MSVC 2015 + LLVM 4.0 RC2 problem compiling LLVMPipe of Mesa 17.0 |
| 8:24PM |
1 |
Code compaction |
| 4:09AM |
0 |
Bundling MachineInstr instructions before register allocation seems to always give errors |
| 4:00AM |
0 |
Understanding SlotIndexes |
| 3:01AM |
0 |
Understanding SlotIndexes |
| |
| Thursday February 23 2017 |
| Time | Replies | Subject |
|---|
| 10:13PM |
2 |
[Proposal][RFC] Epilog loop vectorization |
| 9:02PM |
0 |
Adding register class for just one instruction |
| 7:49PM |
0 |
Any thoughts about preserving backend dependence? |
| 6:48PM |
0 |
llvm-lit: 2>&1 and FileCheck |
| 6:16PM |
1 |
System hangs during last stages of LLVM build | Tips on speeding it up ? |
| 6:16PM |
4 |
RFC: Generalize means the sanitizers work with memory |
| 5:45PM |
0 |
System hangs during last stages of LLVM build | Tips on speeding it up ? |
| 5:41PM |
0 |
System hangs during last stages of LLVM build | Tips on speeding it up ? |
| 5:21PM |
5 |
System hangs during last stages of LLVM build | Tips on speeding it up ? |
| 4:43PM |
1 |
Is OrcJIT compile-on-demand thread safe? |
| 2:53PM |
4 |
llvm-lit: 2>&1 and FileCheck |
| 2:47PM |
1 |
MSVC 2015 + LLVM 4.0 RC2 problem compiling LLVMPipe of Mesa 17.0 |
| 2:45PM |
2 |
Bundling MachineInstr instructions before register allocation seems to always give errors |
| 2:41PM |
0 |
Post-register allocation MachineLICM does not optimize loops |
| 1:19PM |
0 |
Source to Source compiler to implement "#pragma forceinline [recursive]" using clang |
| 12:38PM |
0 |
Help required, Target Specifc SDNode getting optimized by ISel DAG |
| 10:58AM |
0 |
LLVM social in Sweden? |
| 10:25AM |
1 |
RFC: Adding llvm::ThinStream |
| 10:22AM |
0 |
Help required, Target Specifc SDNode getting optimized by ISel DAG |
| 9:14AM |
0 |
[lld] elf linker creates undefined empty symbol |
| |
| Wednesday February 22 2017 |
| Time | Replies | Subject |
|---|
| 10:36PM |
0 |
Users of MIPS and PowerPC backends in production-class projects? |
| 10:34PM |
0 |
[4.0.0 Release] Current status |
| 9:45PM |
2 |
Users of MIPS and PowerPC backends in production-class projects? |
| 9:35PM |
1 |
[Job Ad] Compiler Engineer positions at Intel |
| 9:12PM |
1 |
RFC: Adding llvm::ThinStream |
| 8:28PM |
0 |
RFC: Adding llvm::ThinStream |
| 7:57PM |
0 |
RFC: Adding llvm::ThinStream |
| 7:29PM |
2 |
RFC: Adding llvm::ThinStream |
| 7:03PM |
0 |
[Job Ad] Compiler Engineer positions at Intel |
| 6:37PM |
0 |
tooling libraries missing in Windows download |
| 6:13PM |
0 |
RFC: Adding llvm::ThinStream |
| 5:52PM |
0 |
[Proposal][RFC] Epilog loop vectorization |
| 5:31PM |
2 |
[Job Ad] Compiler Engineer positions at Intel |
| 2:44PM |
0 |
Users of MIPS and PowerPC backends in production-class projects? |
| 2:28PM |
0 |
Orc JIT stub size |
| 2:14PM |
2 |
[lld] elf linker creates undefined empty symbol |
| 1:54PM |
3 |
[EuroLLVM] Program available! Hacker's Lab topics wanted! |
| 1:17PM |
1 |
Help required, Target Specifc SDNode getting optimized by ISel DAG |
| 12:56PM |
0 |
LLVM social in Sweden? |
| 12:22PM |
0 |
[lld] elf linker creates undefined empty symbol |
| 11:47AM |
2 |
[lld] elf linker creates undefined empty symbol |
| 11:12AM |
0 |
[lld] elf linker creates undefined empty symbol |
| 10:56AM |
0 |
Users of MIPS and PowerPC backends in production-class projects? |
| 9:57AM |
3 |
[Proposal][RFC] Epilog loop vectorization |
| 9:48AM |
6 |
Users of MIPS and PowerPC backends in production-class projects? |
| 7:54AM |
0 |
LLVM GSOC Projects Criteria Consultation (before 2/28) |
| 7:34AM |
2 |
[lld] elf linker creates undefined empty symbol |
| 7:05AM |
1 |
Make MachineLICM PostRA (or PreRa) work only on the inner loop for a loop nest |
| 5:54AM |
0 |
multiprecision add/sub |
| 5:19AM |
0 |
What is the proper usage of LLVMContext? |
| 2:07AM |
1 |
Problem with svn:eol-style |
| 12:41AM |
0 |
Problem with svn:eol-style |
| |
| Tuesday February 21 2017 |
| Time | Replies | Subject |
|---|
| 11:49PM |
0 |
LLVM buildmaster will be updated and restarted tonight |
| 10:05PM |
0 |
[lld] elf linker creates undefined empty symbol |
| 9:59PM |
0 |
LLVM nightly installer for Windows is missing lldb's python35.dll |
| 9:36PM |
2 |
tooling libraries missing in Windows download |
| 9:22PM |
3 |
[lld] elf linker creates undefined empty symbol |
| 7:33PM |
0 |
[lld] elf linker creates undefined empty symbol |
| 6:56PM |
0 |
[lld] Has anybody ever run into the Solaris linker before? |
| 6:48PM |
0 |
Fwd: buildbot failure in LLVM on clang-ppc64be-linux |
| 6:28PM |
2 |
Problem with svn:eol-style |
| 6:23PM |
3 |
RFC: Setting MachineInstr flags through storeRegToStackSlot |
| 6:18PM |
0 |
Error at Pre-regalloc Machine LICM: "getVRegDef assumes a single definition or no definition"' failed. |
| 5:39PM |
0 |
Linker error with XRay & GCC/libstdc++ 6.1 |
| 4:37PM |
0 |
LLVM Pass - Backend or IR |
| 2:15PM |
3 |
What is the proper usage of LLVMContext? |
| 1:10PM |
3 |
[lld] elf linker creates undefined empty symbol |
| 11:35AM |
0 |
Linking Linux kernel with LLD |
| 11:25AM |
2 |
Linking Linux kernel with LLD |
| 11:17AM |
0 |
Linking Linux kernel with LLD |
| 7:48AM |
1 |
An alternative way to resolve complex LSR solutions (need perf testing) |
| 7:26AM |
2 |
Linking Linux kernel with LLD |
| 7:16AM |
0 |
Linking Linux kernel with LLD |
| 3:15AM |
2 |
Error at Pre-regalloc Machine LICM: "getVRegDef assumes a single definition or no definition"' failed. |
| 1:39AM |
1 |
Pre-register allocation callback |
| |
| Monday February 20 2017 |
| Time | Replies | Subject |
|---|
| 9:38PM |
2 |
LLVM nightly installer for Windows is missing lldb's python35.dll |
| 7:21PM |
0 |
LLVM Weekly - #164, Feb 20th 2017 |
| 7:14PM |
0 |
Inlining with the ORC JIT |
| 5:44PM |
2 |
Inlining with the ORC JIT |
| 5:34PM |
1 |
[GreenDragon] Working on Green Dragon today |
| 4:38PM |
1 |
Question on GlobalISel Intermediate invariants |
| 4:25PM |
0 |
x86 and GPU backend support for irregular accesses |
| 4:19PM |
3 |
x86 and GPU backend support for irregular accesses |
| 3:51PM |
2 |
Linking Linux kernel with LLD |
| 3:00PM |
0 |
Question on GlobalISel Intermediate invariants |
| 2:26PM |
2 |
LLVM GSOC Projects Criteria Consultation (before 2/28) |
| 2:14PM |
2 |
Question on GlobalISel Intermediate invariants |
| 1:59PM |
0 |
Linking Linux kernel with LLD |
| 1:48PM |
0 |
Help Lowering floating point conditional branch to library call |
| 1:30PM |
1 |
vectorization and vliw(very long instruction word) |
| 12:47PM |
0 |
vectorization and vliw(very long instruction word) |
| 9:09AM |
1 |
Participating in GSoC 2017 |
| 8:05AM |
1 |
llvm-dev Digest, Vol 152, Issue 83 |
| 2:37AM |
2 |
vectorization and vliw(very long instruction word) |
| |
| Sunday February 19 2017 |
| Time | Replies | Subject |
|---|
| 7:29PM |
0 |
Specify special cases of delay slots in the back end |
| 1:49PM |
0 |
Participating in GSoC 2017 |
| 1:38PM |
0 |
Extract injected metadata value from Function metadata |
| 8:12AM |
2 |
Linking Linux kernel with LLD |
| 3:20AM |
1 |
Asan self host problems: Failed to deallocate |
| 1:09AM |
5 |
RFC: Adding llvm::ThinStream |
| 1:07AM |
2 |
[MemorySSA] inserting or removing memory instructions |
| 12:05AM |
0 |
[MemorySSA] inserting or removing memory instructions |
| |
| Saturday February 18 2017 |
| Time | Replies | Subject |
|---|
| 9:37PM |
1 |
LLVM/CMake: in-source-tree and out-of-source tree CMake configs for the same project. |
| 4:11PM |
0 |
Vector trunc code generation difference between llvm-3.9 and 4.0 |
| 11:34AM |
2 |
[lld] Has anybody ever run into the Solaris linker before? |
| 9:03AM |
0 |
Linking Linux kernel with LLD |
| 7:33AM |
2 |
Vector trunc code generation difference between llvm-3.9 and 4.0 |
| 3:08AM |
0 |
Question about compatibility of SafeStack |
| 2:10AM |
0 |
LLVM GSOC Projects Criteria Consultation (before 2/28) |
| 1:27AM |
2 |
[RFC] Using Intel MPX to harden SafeStack |
| |
| Friday February 17 2017 |
| Time | Replies | Subject |
|---|
| 11:14PM |
0 |
RFC: Setting MachineInstr flags through storeRegToStackSlot |
| 10:39PM |
0 |
FYI, Phabricator is really slow due to HN about LLD |
| 10:21PM |
0 |
when will LLD be included with LLVM releases? |
| 9:58PM |
1 |
[lldb-dev] FYI, Phabricator is really slow due to HN about LLD |
| 9:56PM |
2 |
[MemorySSA] inserting or removing memory instructions |
| 9:55PM |
1 |
(RFC) Adjusting default loop fully unroll threshold |
| 9:37PM |
0 |
[MemorySSA] inserting or removing memory instructions |
| 9:37PM |
0 |
[lldb-dev] FYI, Phabricator is really slow due to HN about LLD |
| 9:19PM |
2 |
[MemorySSA] inserting or removing memory instructions |
| 7:52PM |
2 |
multiprecision add/sub |
| 7:33PM |
1 |
[DebugInfo][DWARFv5] should -gdwarf-5 imply usage of .debug_names? |
| 7:23PM |
5 |
FYI, Phabricator is really slow due to HN about LLD |
| 7:23PM |
1 |
RFC: Setting MachineInstr flags through storeRegToStackSlot |
| 7:17PM |
0 |
Intel MPX support (instrumentation pass similar to gcc's Pointer Checker) |
| 7:03PM |
0 |
Vector trunc code generation difference between llvm-3.9 and 4.0 |
| 7:03PM |
0 |
LLVM GSOC Projects Criteria Consultation |
| 6:34PM |
0 |
[DebugInfo][DWARFv5] should -gdwarf-5 imply usage of .debug_names? |
| 6:27PM |
3 |
when will LLD be included with LLVM releases? |
| 4:58PM |
1 |
LLVM Social Berlin #6, February 23rd |
| 4:38PM |
2 |
Vector trunc code generation difference between llvm-3.9 and 4.0 |
| 4:31PM |
3 |
Linking Linux kernel with LLD |
| 4:21PM |
0 |
Vector trunc code generation difference between llvm-3.9 and 4.0 |
| 3:29PM |
0 |
RFC: Setting MachineInstr flags through storeRegToStackSlot |
| 3:12PM |
0 |
Intel MPX support (instrumentation pass similar to gcc's Pointer Checker) |
| 2:42PM |
0 |
(RFC) Adjusting default loop fully unroll threshold |
| 2:30PM |
1 |
Print Register Liveness Information |
| 1:59PM |
2 |
[DebugInfo][DWARFv5] should -gdwarf-5 imply usage of .debug_names? |
| 12:26PM |
4 |
LLVM social in Sweden? |
| 11:33AM |
7 |
RFC: Setting MachineInstr flags through storeRegToStackSlot |
| 10:07AM |
0 |
LLVM social in Italy anyone interested? |
| 10:04AM |
6 |
Intel MPX support (instrumentation pass similar to gcc's Pointer Checker) |
| 9:48AM |
3 |
LLVM social in Italy anyone interested? |
| 9:25AM |
0 |
LLVM social Belgium - 6th of March 2017 |
| 7:08AM |
2 |
LLVM Bugzilla MOVED to bugs.llvm.org |
| 6:16AM |
6 |
LLVM GSOC Projects Criteria Consultation (before 2/28) |
| 3:48AM |
1 |
Help needed to define and handle custom pragma #mypragma |
| 3:06AM |
0 |
(RFC) Adjusting default loop fully unroll threshold |
| 2:58AM |
0 |
llvm vliw and vectorization |
| 2:58AM |
0 |
LLVM Bugzilla MOVED to bugs.llvm.org |
| 2:38AM |
0 |
回复: How to catch EXCEPTION_ACCESS_VIOLATION exceptions on win64 |
| 2:34AM |
2 |
LLVM Bugzilla MOVED to bugs.llvm.org |
| 2:33AM |
0 |
LLVM Bugzilla MOVED to bugs.llvm.org |
| 1:43AM |
2 |
(RFC) Adjusting default loop fully unroll threshold |
| 1:01AM |
0 |
Asan self host problems: Failed to deallocate |
| 12:41AM |
0 |
(RFC) Adjusting default loop fully unroll threshold |
| |
| Thursday February 16 2017 |
| Time | Replies | Subject |
|---|
| 11:48PM |
2 |
LLVM Bugzilla MOVED to bugs.llvm.org |
| 11:45PM |
4 |
(RFC) Adjusting default loop fully unroll threshold |
| 10:48PM |
0 |
Print Register Liveness Information |
| 10:32PM |
2 |
Print Register Liveness Information |
| 9:21PM |
0 |
Print Register Liveness Information |
| 8:46PM |
2 |
Print Register Liveness Information |
| 7:40PM |
0 |
Green Dragon network issues |
| 7:35PM |
1 |
Unsigned int displaying as negative |
| 7:23PM |
0 |
Unsigned int displaying as negative |
| 6:41PM |
3 |
Linker error with XRay & GCC/libstdc++ 6.1 |
| 6:15PM |
3 |
Unsigned int displaying as negative |
| 6:08PM |
0 |
multiprecision add/sub |
| 5:12PM |
2 |
multiprecision add/sub |
| 4:54PM |
0 |
getMetadata for function |
| 4:51PM |
1 |
Outlining in JIT LLVM |
| 4:21PM |
0 |
Can we keep debug information of local variable when in the optimization condition? |
| 4:17PM |
0 |
Outlining in JIT LLVM |
| 3:18PM |
2 |
Can we keep debug information of local variable when in the optimization condition? |
| 2:49PM |
0 |
Unsigned int displaying as negative |
| 2:37PM |
2 |
Compilation doesn't finish when building with clang 4.0.0 (was: [cfe-dev] [4.0.0 Release] Release Candidate 2 source and binaries available) |
| 10:52AM |
2 |
Outlining in JIT LLVM |
| 10:46AM |
0 |
(RFC) Adjusting default loop fully unroll threshold |
| 9:48AM |
2 |
How to catch EXCEPTION_ACCESS_VIOLATION exceptions on win64 |
| 6:03AM |
0 |
Help with LLVM exceptions |
| 3:44AM |
0 |
multiprecision add/sub |
| 1:08AM |
2 |
LLVMBuildPhi() circular dependency problem |
| 1:02AM |
2 |
Unsigned int displaying as negative |
| 12:24AM |
2 |
multiprecision add/sub |
| |
| Wednesday February 15 2017 |
| Time | Replies | Subject |
|---|
| 10:59PM |
1 |
multiprecision add/sub |
| 10:28PM |
0 |
multiprecision add/sub |
| 10:22PM |
4 |
multiprecision add/sub |
| 10:16PM |
0 |
Unsigned int displaying as negative |
| 10:15PM |
0 |
[GlobalISel] Quick Status |
| 9:58PM |
0 |
Unsigned int displaying as negative |
| 9:52PM |
0 |
Unsigned int displaying as negative |
| 9:51PM |
1 |
Unsupported expression in static initializer? |
| 9:40PM |
0 |
Unsupported expression in static initializer? |
| 9:22PM |
2 |
Unsupported expression in static initializer? |
| 9:11PM |
0 |
Compilation doesn't finish when building with clang 4.0.0 (was: [cfe-dev] [4.0.0 Release] Release Candidate 2 source and binaries available) |
| 9:09PM |
2 |
Asan self host problems: Failed to deallocate |
| 9:04PM |
0 |
Problem using Boost Filesystem with Clang |
| 8:44PM |
0 |
FW: [Dwarf-Discuss] DWARF Version 5 Standard Released |
| 8:29PM |
1 |
Unsigned int displaying as negative |
| 8:14PM |
0 |
Unsigned int displaying as negative |
| 7:48PM |
5 |
Unsigned int displaying as negative |
| 7:38PM |
0 |
Unsigned int displaying as negative |
| 7:37PM |
4 |
Unsigned int displaying as negative |
| 7:24PM |
0 |
Unsigned int displaying as negative |
| 7:00PM |
1 |
DWARF: Should type units be referenced by signature or declaration? |
| 6:54PM |
2 |
Unsigned int displaying as negative |
| 6:44PM |
0 |
Unsigned int displaying as negative |
| 6:30PM |
0 |
Unsigned int displaying as negative |
| 6:28PM |
2 |
Unsigned int displaying as negative |
| 6:24PM |
0 |
Unsigned int displaying as negative |
| 6:19PM |
6 |
Unsigned int displaying as negative |
| 6:10PM |
2 |
(RFC) Adjusting default loop fully unroll threshold |
| 6:01PM |
2 |
Problem using Boost Filesystem with Clang |
| 5:50PM |
1 |
[cfe-dev] [4.0.0 Release] Release Candidate 2 source and binaries available |
| 2:49PM |
1 |
Help lowering byte wise compare instruction |
| 12:44PM |
2 |
RFC: Representing unions in TBAA |
| 11:43AM |
0 |
[cfe-dev] [4.0.0 Release] Release Candidate 2 source and binaries available |
| 10:24AM |
2 |
[cfe-dev] [4.0.0 Release] Release Candidate 2 source and binaries available |
| 6:12AM |
0 |
(RFC) JumpMaps: switch statement optimization |
| 4:22AM |
0 |
RFC: Representing unions in TBAA |
| 3:31AM |
0 |
DWARF: Should type units be referenced by signature or declaration? |
| |
| Tuesday February 14 2017 |
| Time | Replies | Subject |
|---|
| 8:53PM |
0 |
(RFC) Adjusting default loop fully unroll threshold |
| 8:44PM |
1 |
An option switching LSR to choose solution with minimum instructions |
| 8:28PM |
0 |
Help with Analysis pass design |
| 7:58PM |
0 |
[4.0.0 Release] Release Candidate 2 source and binaries available |
| 7:56PM |
0 |
[4.0.0 Release] Release Candidate 1 source and binaries available |
| 7:36PM |
0 |
(RFC) Adjusting default loop fully unroll threshold |
| 7:21PM |
0 |
Adding FP environment register modeling for constrained FP nodes |
| 6:38PM |
3 |
(RFC) JumpMaps: switch statement optimization |
| 6:25PM |
2 |
Adding FP environment register modeling for constrained FP nodes |
| 6:21PM |
0 |
Ensuring chain dependencies with expansion to libcalls |
| 4:32PM |
0 |
[RFC] [LV] Introducing VPlan to model the vectorized code and drive its transformation |
| 4:16PM |
0 |
generated HWEncoding based register decoders |
| 3:05PM |
2 |
RFC: Representing unions in TBAA |
| 1:51PM |
0 |
RFC: Representing unions in TBAA |
| 1:47PM |
0 |
(RFC) JumpMaps: switch statement optimization |
| 1:28PM |
2 |
(RFC) JumpMaps: switch statement optimization |
| 12:10PM |
0 |
addRequired() + getAnalysis() for new / non-legacy pass manager |
| 11:27AM |
2 |
Ensuring chain dependencies with expansion to libcalls |
| 10:51AM |
2 |
addRequired() + getAnalysis() for new / non-legacy pass manager |
| 9:53AM |
0 |
(RFC) JumpMaps: switch statement optimization |
| 8:21AM |
1 |
HOW TO ACCESS THE LHS PART OF LOAD/ALLOCA INSTRUCTION. |
| 3:39AM |
2 |
RFC: Representing unions in TBAA |
| 2:21AM |
0 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 2:06AM |
3 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 1:58AM |
0 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 1:57AM |
0 |
Bugzilla invalid certificate issues |
| 1:56AM |
2 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 1:48AM |
0 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 1:37AM |
2 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 1:31AM |
0 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 1:26AM |
2 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 1:20AM |
0 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 1:17AM |
0 |
opt-viewer demo |
| 12:47AM |
0 |
LLVM buildmaster will be updated and restarted tonight |
| 12:46AM |
2 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 12:23AM |
0 |
(RFC) JumpMaps: switch statement optimization |
| 12:17AM |
0 |
Asan self host problems: Failed to deallocate |
| |
| Monday February 13 2017 |
| Time | Replies | Subject |
|---|
| 11:52PM |
1 |
[GlobalISel] Quick Status |
| 11:30PM |
0 |
[GlobalISel] Quick Status |
| 10:48PM |
0 |
compiler-rt linux-arm builtins/clear_cache.c depends on kernel headers |
| 10:17PM |
2 |
(RFC) Adjusting default loop fully unroll threshold |
| 9:59PM |
0 |
(RFC) Adjusting default loop fully unroll threshold |
| 9:37PM |
1 |
using getTargetInsertSubreg in DAG |
| 9:34PM |
0 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 9:24PM |
2 |
Bugzilla invalid certificate issues |
| 9:16PM |
2 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 9:02PM |
1 |
New IRC Buildbot Channel #llvm-build |
| 8:57PM |
0 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 8:52PM |
2 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 8:41PM |
0 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 8:33PM |
2 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 8:08PM |
0 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 7:40PM |
1 |
[GlobalISel] Quick Status |
| 7:24PM |
0 |
LLVM JIT reentrant? |
| 7:12PM |
0 |
LLVM Bugzilla MOVED to bugs.llvm.org |
| 6:56PM |
5 |
(RFC) Adjusting default loop fully unroll threshold |
| 6:46PM |
0 |
LLVM Bugzilla MOVED to bugs.llvm.org |
| 6:07PM |
0 |
RFC: Representing unions in TBAA |
| 4:56PM |
3 |
RFC: A new llvm-dlltool driver and llvm-lib driver improvements |
| 4:29PM |
0 |
(RFC) Adjusting default loop fully unroll threshold |
| 4:23PM |
0 |
[GlobalISel] Quick Status |
| 3:55PM |
0 |
I'd like to translate the Kaleidoscope tutorial to D language, where should I ask for permission? |
| 3:42PM |
0 |
ARM Backend: Emit conditional move |
| 1:11PM |
5 |
(RFC) JumpMaps: switch statement optimization |
| 12:25PM |
1 |
LLVM Weekly - #163, Feb 13th 2017 |
| 9:36AM |
2 |
ARM Backend: Emit conditional move |
| 7:23AM |
2 |
RFC: Representing unions in TBAA |
| 6:50AM |
0 |
RFC: Representing unions in TBAA |
| 6:00AM |
2 |
I'd like to translate the Kaleidoscope tutorial to D language, where should I ask for permission? |
| 4:01AM |
2 |
RFC: Representing unions in TBAA |
| 3:09AM |
4 |
LLVM Bugzilla MOVED to bugs.llvm.org |
| 3:02AM |
1 |
Enforcing in post-RA scheduling to keep (two) MachineInstrs together |
| |
| Sunday February 12 2017 |
| Time | Replies | Subject |
|---|
| 11:18PM |
2 |
compiler-rt linux-arm builtins/clear_cache.c depends on kernel headers |
| 10:26PM |
0 |
compiler-rt linux-arm builtins/clear_cache.c depends on kernel headers |
| 9:43PM |
0 |
Regarding LLVM JIT Project |
| 10:57AM |
0 |
Finding relocation symbols |
| 3:40AM |
0 |
LLVM buildmaster will be updated and restarted tonight |
| 2:10AM |
2 |
Pre-RA scheduler does not generate NOPs when getHazardType() returns NoopHazard |
| |
| Saturday February 11 2017 |
| Time | Replies | Subject |
|---|
| 8:28PM |
0 |
Bugzilla invalid certificate issues |
| 6:15PM |
1 |
Kaleidoscope tutorial: comments, corrections and Windows support |
| 5:42PM |
0 |
How do I find the function pointers for tests from the LLVM IR code of a Rust program? |
| 12:39PM |
2 |
Specify special cases of delay slots in the back end |
| 5:41AM |
2 |
Asan self host problems: Failed to deallocate |
| 12:27AM |
3 |
Bugzilla invalid certificate issues |
| |
| Friday February 10 2017 |
| Time | Replies | Subject |
|---|
| 11:53PM |
0 |
(RFC) Adjusting default loop fully unroll threshold |
| 11:23PM |
4 |
(RFC) Adjusting default loop fully unroll threshold |
| 11:21PM |
0 |
(RFC) Adjusting default loop fully unroll threshold |
| 10:23PM |
0 |
[cfe-dev] [Release-testers] [4.0.0 Release] Release Candidate 2 has been tagged |
| 9:33PM |
0 |
Specify special cases of delay slots in the back end |
| 9:28PM |
1 |
Bugzilla invalid certificate issues |
| 9:26PM |
0 |
Enforcing in post-RA scheduling to keep (two) MachineInstrs together |
| 8:52PM |
3 |
Enforcing in post-RA scheduling to keep (two) MachineInstrs together |
| 8:42PM |
2 |
Specify special cases of delay slots in the back end |
| 6:59PM |
2 |
generated HWEncoding based register decoders |
| 4:58PM |
0 |
Stripping Debug Locations on cross BB moves, part 2 (PR31891) |
| 4:47PM |
0 |
RFC: Generic IR reductions |
| 3:10PM |
1 |
Add a custom intrinsic to the ARM backend |
| 2:58PM |
0 |
generated HWEncoding based register decoders |
| 2:30PM |
0 |
Add a custom intrinsic to the ARM backend |
| 1:00PM |
1 |
Problem ScheduleDAG on PowerPC, X86 works fine. |
| 12:14PM |
1 |
sanitize=cfi-icall in real life application on x86 and ARM |
| 11:56AM |
2 |
[cfe-dev] [Release-testers] [4.0.0 Release] Release Candidate 2 has been tagged |
| 11:38AM |
0 |
[cfe-dev] [Release-testers] [4.0.0 Release] Release Candidate 2 has been tagged |
| 10:12AM |
2 |
Add a custom intrinsic to the ARM backend |
| 10:00AM |
2 |
RFC: Generic IR reductions |
| 9:33AM |
1 |
llvm-lit |
| 5:22AM |
1 |
Improving the split heuristics for the Greedy Register Allocator |
| 3:58AM |
0 |
[RFC] Proposing libcxx-config.py: a configuration tool for building and using libc++ |
| 3:33AM |
0 |
LLVM buildmaster will be updated and restarted tonight |
| 2:37AM |
1 |
help me understand how nounwind attribute on functions works? |
| 2:25AM |
0 |
help me understand how nounwind attribute on functions works? |
| 2:16AM |
2 |
help me understand how nounwind attribute on functions works? |
| 1:16AM |
2 |
Stripping Debug Locations on cross BB moves, part 2 (PR31891) |
| 12:47AM |
1 |
Compatibility issue with go |
| 12:18AM |
2 |
generated HWEncoding based register decoders |
| 12:18AM |
3 |
[RFC] Proposing libcxx-config.py: a configuration tool for building and using libc++ |
| 12:12AM |
0 |
Compatibility issue with go |
| 12:11AM |
0 |
Linking Linux kernel with LLD |
| 12:09AM |
0 |
Stripping Debug Locations on cross BB moves, part 2 (PR31891) |
| 12:02AM |
2 |
Compatibility issue with go |
| |
| Thursday February 9 2017 |
| Time | Replies | Subject |
|---|
| 11:42PM |
0 |
Specify special cases of delay slots in the back end |
| 10:46PM |
2 |
Specify special cases of delay slots in the back end |
| 10:33PM |
2 |
[Release-testers] [4.0.0 Release] Release Candidate 2 has been tagged |
| 10:23PM |
0 |
[Release-testers] [4.0.0 Release] Release Candidate 2 has been tagged |
| 9:46PM |
4 |
[4.0.0] Release notes nag email |
| 7:24PM |
0 |
Atom editor crashes when linking lldb |
| 6:32PM |
1 |
help me understand how nounwind attribute on functions works? |
| 5:55PM |
0 |
[Release-testers] [4.0.0 Release] Release Candidate 2 has been tagged |
| 5:40PM |
0 |
help me understand how nounwind attribute on functions works? |
| 5:31PM |
0 |
RFC: Generic IR reductions |
| 5:12PM |
2 |
help me understand how nounwind attribute on functions works? |
| 4:41PM |
0 |
help me understand how nounwind attribute on functions works? |
| 4:33PM |
1 |
[cfe-dev] lli: LLVM ERROR: Cannot select: X86ISD::WrapperRIP TargetGlobalTLSAddress:i64 |
| 4:28PM |
2 |
Stripping Debug Locations on cross BB moves, part 2 (PR31891) |
| 3:02PM |
0 |
Using Phabricator for all LLVM development |
| 2:49PM |
2 |
Using Phabricator for all LLVM development |
| 1:59PM |
0 |
Clang-Format and Lambdas |
| 10:21AM |
0 |
Problem ScheduleDAG on PowerPC, X86 works fine. |
| 9:27AM |
4 |
Linking Linux kernel with LLD |
| 7:13AM |
1 |
Status of the AVR backend |
| 7:05AM |
1 |
[RFC] Queries for LLVM version |
| 7:00AM |
1 |
ShuffleKind SK_ExtractSubvector |
| 6:17AM |
0 |
Improving the split heuristics for the Greedy Register Allocator |
| 4:48AM |
2 |
Problem ScheduleDAG on PowerPC, X86 works fine. |
| 4:15AM |
2 |
Improving the split heuristics for the Greedy Register Allocator |
| 1:45AM |
4 |
help me understand how nounwind attribute on functions works? |
| 12:54AM |
0 |
Linking Linux kernel with LLD |
| 12:33AM |
7 |
[4.0.0 Release] Release Candidate 2 has been tagged |
| 12:28AM |
0 |
Problem ScheduleDAG on PowerPC, X86 works fine. |
| |
| Wednesday February 8 2017 |
| Time | Replies | Subject |
|---|
| 8:19PM |
3 |
Problem ScheduleDAG on PowerPC, X86 works fine. |
| 7:40PM |
0 |
[cfe-dev] lli: LLVM ERROR: Cannot select: X86ISD::WrapperRIP TargetGlobalTLSAddress:i64 |
| 6:58PM |
0 |
help me understand how nounwind attribute on functions works? |
| 6:32PM |
0 |
Stripping Debug Locations on cross BB moves, part 2 (PR31891) |
| 6:17PM |
2 |
Stripping Debug Locations on cross BB moves, part 2 (PR31891) |
| 6:10PM |
0 |
ShuffleKind SK_ExtractSubvector |
| 5:56PM |
0 |
Stripping Debug Locations on cross BB moves, part 2 (PR31891) |
| 5:50PM |
3 |
[cfe-dev] lli: LLVM ERROR: Cannot select: X86ISD::WrapperRIP TargetGlobalTLSAddress:i64 |
| 5:44PM |
2 |
Stripping Debug Locations on cross BB moves, part 2 (PR31891) |
| 5:36PM |
0 |
Stripping Debug Locations on cross BB moves, part 2 (PR31891) |
| 5:25PM |
3 |
Stripping Debug Locations on cross BB moves, part 2 (PR31891) |
| 4:02PM |
0 |
[RFC] Queries for LLVM version |
| 3:59PM |
3 |
Linking Linux kernel with LLD |
| 3:43PM |
2 |
[RFC] Queries for LLVM version |
| 2:56PM |
0 |
[RFC] Queries for LLVM version |
| 2:53PM |
0 |
[cfe-dev] lli: LLVM ERROR: Cannot select: X86ISD::WrapperRIP TargetGlobalTLSAddress:i64 |
| 2:35PM |
2 |
ShuffleKind SK_ExtractSubvector |
| 1:51PM |
2 |
[RFC] Queries for LLVM version |
| 12:57PM |
2 |
[cfe-dev] lli: LLVM ERROR: Cannot select: X86ISD::WrapperRIP TargetGlobalTLSAddress:i64 |
| 9:18AM |
0 |
[RFC] Queries for LLVM version |
| 6:24AM |
2 |
(RFC) Adjusting default loop fully unroll threshold |
| 5:20AM |
1 |
Code Owner for the LLVM Bitcode |
| 4:02AM |
0 |
[RFC] Using Intel MPX to harden SafeStack |
| 12:16AM |
2 |
llc -O3 generates basic blocks that end without jump |
| 12:05AM |
4 |
[RFC] Using Intel MPX to harden SafeStack |
| |
| Tuesday February 7 2017 |
| Time | Replies | Subject |
|---|
| 11:44PM |
2 |
[RFC] Queries for LLVM version |
| 11:29PM |
0 |
(RFC) Adjusting default loop fully unroll threshold |
| 11:23PM |
0 |
Clang option to provide list of target-subarchs. |
| 11:18PM |
0 |
Clang option to provide list of target-subarchs. |
| 11:12PM |
0 |
[RFC] Queries for LLVM version |
| 11:04PM |
2 |
[RFC] Queries for LLVM version |
| 10:44PM |
0 |
Problem ScheduleDAG on PowerPC, X86 works fine. |
| 10:26PM |
2 |
(RFC) Adjusting default loop fully unroll threshold |
| 10:14PM |
0 |
Using ASAN on C code called from other languages |
| 10:07PM |
2 |
Clang option to provide list of target-subarchs. |
| 9:51PM |
2 |
Problem ScheduleDAG on PowerPC, X86 works fine. |
| 9:39PM |
0 |
Clang option to provide list of target-subarchs. |
| 9:38PM |
0 |
Your help needed: List of LLVM Open Projects 2017 (Modula-3) |
| 8:39PM |
0 |
[RFC] Representing address space information in DWARF |
| 8:15PM |
0 |
Problem ScheduleDAG on PowerPC, X86 works fine. |
| 7:48PM |
2 |
Problem ScheduleDAG on PowerPC, X86 works fine. |
| 7:37PM |
0 |
Code Owner for the LLVM Bitcode |
| 6:03PM |
0 |
FOSDEM LLVM Devroom Videos online |
| 5:40PM |
2 |
Your help needed: List of LLVM Open Projects 2017 (Modula-3) |
| 4:27PM |
0 |
[cfe-dev] lli: LLVM ERROR: Cannot select: X86ISD::WrapperRIP TargetGlobalTLSAddress:i64 |
| 4:19PM |
3 |
[cfe-dev] lli: LLVM ERROR: Cannot select: X86ISD::WrapperRIP TargetGlobalTLSAddress:i64 |
| 3:53PM |
0 |
[cfe-dev] lli: LLVM ERROR: Cannot select: X86ISD::WrapperRIP TargetGlobalTLSAddress:i64 |
| 3:31PM |
0 |
[cfe-dev] lli: LLVM ERROR: Cannot select: X86ISD::WrapperRIP TargetGlobalTLSAddress:i64 |
| 3:13PM |
2 |
[cfe-dev] lli: LLVM ERROR: Cannot select: X86ISD::WrapperRIP TargetGlobalTLSAddress:i64 |
| 1:47PM |
0 |
Clang 5.0 support for armv8 64 bit with neon and auto vectorization |
| 7:55AM |
0 |
[RFC][PIR] Parallel LLVM IR -- Stage 0 -- IR extension |
| 7:33AM |
2 |
Using ASAN on C code called from other languages |
| 7:02AM |
0 |
Kaleidoscope tutorial: comments, corrections and Windows support |
| 4:14AM |
0 |
buildbot numbers for the week of 01/15/2017 - 01/21/2017 |
| 4:11AM |
0 |
LLBM master is back to work |
| 2:39AM |
2 |
Clang option to provide list of target-subarchs. |
| 2:19AM |
1 |
LLVM buildmaster is unavailable due to power outage in our area |
| 1:12AM |
1 |
Your help needed: List of LLVM Open Projects 2017 |
| |
| Monday February 6 2017 |
| Time | Replies | Subject |
|---|
| 11:12PM |
0 |
Using ASAN on C code called from other languages |
| 11:07PM |
3 |
Kaleidoscope tutorial: comments, corrections and Windows support |
| 9:49PM |
0 |
Adding Extended-SSA to LLVM |
| 8:55PM |
0 |
Your help needed: List of LLVM Open Projects 2017 |
| 7:07PM |
2 |
Your help needed: List of LLVM Open Projects 2017 |
| 6:29PM |
0 |
Your help needed: List of LLVM Open Projects 2017 |
| 5:50PM |
2 |
this ir code segfaults llvm in trunk |
| 5:48PM |
1 |
this ir code segfaults llvm in trunk |
| 5:36PM |
0 |
this ir code segfaults llvm in trunk |
| 1:53PM |
0 |
LLVM Weekly - #162, Feb 6th 2017 |
| 7:41AM |
4 |
this ir code segfaults llvm in trunk |
| 7:35AM |
2 |
Using ASAN on C code called from other languages |
| 3:13AM |
0 |
Your help needed: List of LLVM Open Projects 2017 (Modula-3) |
| 12:26AM |
2 |
Adding Extended-SSA to LLVM |
| |
| Sunday February 5 2017 |
| Time | Replies | Subject |
|---|
| 11:41PM |
0 |
Adding Extended-SSA to LLVM |
| 9:32PM |
0 |
[cfe-dev] RFC: Add a way to interleave source code in assembler output |
| 9:25PM |
3 |
Adding Extended-SSA to LLVM |
| 8:25PM |
0 |
Adding Extended-SSA to LLVM |
| 4:32PM |
2 |
help me understand how nounwind attribute on functions works? |
| 4:19PM |
0 |
clang/llvm support for %= in inline assembly |
| 1:05PM |
2 |
clang/llvm support for %= in inline assembly |
| 9:50AM |
0 |
clang/llvm support for %= in inline assembly |
| 6:30AM |
2 |
clang/llvm support for %= in inline assembly |
| 5:36AM |
2 |
Clang 5.0 support for armv8 64 bit with neon and auto vectorization |
| 1:52AM |
1 |
Clang 5.0 support for armv8 64 bit with neon and auto vectorization |
| 1:21AM |
0 |
How to get assembly opcode mnemonic(s) corresponding to a MachineInstr? |
| |
| Saturday February 4 2017 |
| Time | Replies | Subject |
|---|
| 10:19PM |
2 |
How to get assembly opcode mnemonic(s) corresponding to a MachineInstr? |
| 10:04PM |
0 |
Wrong relocation emitted when building shared libraries with Control Flow Integrity |
| 9:59PM |
0 |
CFI, Safe-Stack, and -fno-sanitize-trap |
| 6:45PM |
0 |
[OT] Fortran + LLVM |
| 1:52PM |
0 |
16-bit bytes for AsmPrinter/DWARF |
| 12:08PM |
0 |
when will LLD be included with LLVM releases? |
| 8:14AM |
3 |
when will LLD be included with LLVM releases? |
| 7:02AM |
2 |
Wrong relocation emitted when building shared libraries with Control Flow Integrity |
| 3:15AM |
2 |
DWARF: Should type units be referenced by signature or declaration? |
| 2:58AM |
0 |
when will LLD be included with LLVM releases? |
| 1:48AM |
0 |
LLVM buildmaster will be updated and restarted tonight |
| |
| Friday February 3 2017 |
| Time | Replies | Subject |
|---|
| 11:17PM |
1 |
Build status expectations for experimental targets |
| 11:15PM |
0 |
Build status expectations for experimental targets |
| 11:14PM |
2 |
Build status expectations for experimental targets |
| 8:45PM |
0 |
Build status expectations for experimental targets |
| 8:39PM |
2 |
when will LLD be included with LLVM releases? |
| 8:25PM |
0 |
Specify special cases of delay slots in the back end |
| 8:03PM |
0 |
Clang 5.0 support for armv8 64 bit with neon and auto vectorization |
| 7:24PM |
0 |
LLVM Performance Workshop at CGO 2017 |
| 7:03PM |
0 |
RFC: Add a way to interleave source code in assembler output |
| 5:15PM |
3 |
Clang 5.0 support for armv8 64 bit with neon and auto vectorization |
| 5:05PM |
0 |
Clang 5.0 support for armv8 64 bit with neon and auto vectorization |
| 4:31PM |
3 |
RFC: Add a way to interleave source code in assembler output |
| 3:50PM |
2 |
Speculation and control dependent no wrap flags |
| 3:18PM |
2 |
Build status expectations for experimental targets |
| 3:13PM |
2 |
Clang 5.0 support for armv8 64 bit with neon and auto vectorization |
| 3:01PM |
0 |
Clang 5.0 support for armv8 64 bit with neon and auto vectorization |
| 1:49PM |
0 |
Speculation and control dependent no wrap flags |
| 1:28PM |
3 |
Speculation and control dependent no wrap flags |
| 12:18PM |
0 |
Build status expectations for experimental targets |
| 11:25AM |
2 |
RFC: Generic IR reductions |
| 10:37AM |
4 |
Build status expectations for experimental targets |
| 10:15AM |
0 |
RFC: Generic IR reductions |
| 8:48AM |
3 |
Clang 5.0 support for armv8 64 bit with neon and auto vectorization |
| 1:01AM |
2 |
Adding Extended-SSA to LLVM |
| 12:35AM |
0 |
Linking Linux kernel with LLD |
| 12:23AM |
3 |
Linking Linux kernel with LLD |
| |
| Thursday February 2 2017 |
| Time | Replies | Subject |
|---|
| 11:03PM |
2 |
Specify special cases of delay slots in the back end |
| 10:07PM |
0 |
(RFC) Adjusting default loop fully unroll threshold |
| 9:14PM |
0 |
llvm.read_register for %RIP on x86_64 |
| 7:14PM |
1 |
Register allocator behaves differently when compiling with and without -g |
| 6:49PM |
0 |
[X86][AVX512] RFC: make i1 illegal in the Codegen |
| 6:24PM |
0 |
Register allocator behaves differently when compiling with and without -g |
| 5:38PM |
2 |
Register allocator behaves differently when compiling with and without -g |
| 5:37PM |
1 |
Adding Extended-SSA to LLVM |
| 5:18PM |
1 |
Register allocator behaves differently when compiling with and without -g |
| 5:08PM |
0 |
Adding Extended-SSA to LLVM |
| 5:03PM |
0 |
Register allocator behaves differently when compiling with and without -g |
| 4:46PM |
2 |
Register allocator behaves differently when compiling with and without -g |
| 4:42PM |
0 |
Tracking parts of expanded values in optimized debug |
| 4:20PM |
0 |
Register allocator behaves differently when compiling with and without -g |
| 4:17PM |
3 |
Register allocator behaves differently when compiling with and without -g |
| 2:27PM |
1 |
Linking Linux kernel with LLD |
| 1:35PM |
0 |
AOSP buildbot fails with assert in :ScheduleDAGRRList::PickNodeToScheduleBottomUp |
| 1:31PM |
1 |
Fuzzing bitcode reader |
| 1:16PM |
3 |
Tracking parts of expanded values in optimized debug |
| 11:57AM |
0 |
Status of AAP (Embecosm's demonstration architecture)? |
| 9:21AM |
1 |
Question about versioning of LVVM IR |
| 8:38AM |
0 |
Linking Linux kernel with LLD |
| 8:03AM |
1 |
[X86][AVX512] RFC: make i1 illegal in the Codegen |
| 7:20AM |
0 |
Interest in integrating a linux perf JITEventListener? |
| 5:11AM |
2 |
AOSP buildbot fails with assert in :ScheduleDAGRRList::PickNodeToScheduleBottomUp |
| 4:51AM |
4 |
Adding Extended-SSA to LLVM |
| 2:08AM |
2 |
(RFC) Adjusting default loop fully unroll threshold |
| 1:35AM |
0 |
how to verify completeness of the llvm backend |
| 1:06AM |
3 |
RFC: Generic IR reductions |
| 12:57AM |
0 |
(RFC) Adjusting default loop fully unroll threshold |
| 12:47AM |
2 |
(RFC) Adjusting default loop fully unroll threshold |
| 12:33AM |
0 |
(RFC) Adjusting default loop fully unroll threshold |
| |
| Wednesday February 1 2017 |
| Time | Replies | Subject |
|---|
| 10:30PM |
1 |
Fuzzing bitcode reader |
| 10:02PM |
0 |
RFC: Generic IR reductions |
| 10:01PM |
2 |
Linking Linux kernel with LLD |
| 9:22PM |
2 |
RFC: Generic IR reductions |
| 8:52PM |
0 |
RFC: Generic IR reductions |
| 8:27PM |
2 |
RFC: Generic IR reductions |
| 6:36PM |
0 |
[RFC] IR-level Region Annotations |
| 5:50PM |
0 |
Fuzzing bitcode reader |
| 5:45PM |
0 |
[RFC] IR-level Region Annotations |
| 5:34PM |
0 |
[RFC] IR-level Region Annotations |
| 5:27PM |
3 |
Fuzzing bitcode reader |
| 5:19PM |
0 |
Fuzzing bitcode reader |
| 5:07PM |
2 |
Fuzzing bitcode reader |
| 5:01PM |
0 |
Fuzzing bitcode reader |
| 4:58PM |
2 |
how to verify completeness of the llvm backend |
| 4:58PM |
2 |
Fuzzing bitcode reader |
| 4:45PM |
0 |
Fuzzing bitcode reader |
| 4:38PM |
0 |
SafeStack on ARM platform |
| 4:38PM |
0 |
Strange opt error in Value ("replaceAllUses of value with new value of different type!" assertion failure) |
| 4:34PM |
3 |
Fuzzing bitcode reader |
| 4:17PM |
2 |
SafeStack on ARM platform |
| 2:56PM |
1 |
RFC: Generic IR reductions |
| 2:44PM |
1 |
RFC: Generic IR reductions |
| 2:36PM |
0 |
RFC: Generic IR reductions |
| 2:20PM |
0 |
RFC: Generic IR reductions |
| 1:06PM |
2 |
RFC: Generic IR reductions |
| 12:39PM |
0 |
RFC: Generic IR reductions |
| 11:59AM |
2 |
RFC: Generic IR reductions |
| 11:55AM |
2 |
Strange opt error in Value ("replaceAllUses of value with new value of different type!" assertion failure) |
| 10:59AM |
2 |
RFC: Generic IR reductions |
| 10:54AM |
0 |
RFC: Generic IR reductions |
| 10:30AM |
2 |
RFC: Generic IR reductions |
| 10:08AM |
0 |
LLVM Weekly - #161, Jan 30th 2017 |
| 9:58AM |
0 |
RFC: Generic IR reductions |
| 9:38AM |
2 |
RFC: Generic IR reductions |
| 8:27AM |
0 |
RFC: Generic IR reductions |
| 8:21AM |
1 |
getTypeLegalizationCost() |
| 7:29AM |
2 |
[RFC] IR-level Region Annotations |
| 6:59AM |
2 |
[RFC] IR-level Region Annotations |
| 5:03AM |
0 |
[RFC] IR-level Region Annotations |
| 4:53AM |
0 |
LLVM Weekly - #161, Jan 30th 2017 |
| 3:53AM |
2 |
[RFC] IR-level Region Annotations |
| 3:30AM |
0 |
[RFC] IR-level Region Annotations |
| 3:07AM |
1 |
[RFC] IR-level Region Annotations |
| 2:48AM |
0 |
[RFC] IR-level Region Annotations |
| 1:47AM |
2 |
[RFC] IR-level Region Annotations |
| 1:38AM |
0 |
[RFC] IR-level Region Annotations |
| 1:26AM |
1 |
[RFC] IR-level Region Annotations |
| 12:07AM |
2 |
Status of AAP (Embecosm's demonstration architecture)? |