llvm dev - Feb 2017 - Help lowering byte wise compare instruction

Hello LLVM Devs,


Hope you are doing well.
I am implementing LLVM back-end for an architecture which has instruction
that performs byte by byte comparison and stores result for each byte.

pcmpbf rD, rA, rB --> bytewise comparison returning position of first match
in rd

So with this regard I wanted to find similar instruction lowering for nay
other architecture which have similar instruction.
I found some thing similar on PPC. If I am wrong kindly suggest some
example.

I am trying to understand following statement from PPCInstrInfo.td file:
  def CMPRB  : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
                                (ins u1imm:$L, g8rc:$rA, g8rc:$rB),
                                "cmprb $BF, $L, $rA, $rB",
IIC_IntCompare,
[]>,
               Requires<[IsISA3_0]>;
Here I am not able to understand against which DAG pattern this gets
matched ? By doing grep I don't get any code which provide me the required
info.

Basically I want to know which LLVM IR instruction or intrinsic has similar
semantics and then how I can lower it correctly.

Sincerely,
Vivek
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On 02/15/2017 08:49 AM, vivek pandya via llvm-dev wrote:
>
> Hello LLVM Devs,
>
>
> Hope you are doing well.
> I am implementing LLVM back-end for an architecture which has 
> instruction that performs byte by byte comparison and stores result 
> for each byte.
>
> pcmpbf rD, rA, rB --> bytewise comparison returning position of first 
> match in rd
>
> So with this regard I wanted to find similar instruction lowering for 
> nay other architecture which have similar instruction.
> I found some thing similar on PPC. If I am wrong kindly suggest some 
> example.
>
> I am trying to understand following statement from PPCInstrInfo.td file:
>   def CMPRB  : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
>                                 (ins u1imm:$L, g8rc:$rA, g8rc:$rB),
>                                 "cmprb $BF, $L, $rA, $rB", 
> IIC_IntCompare, []>,
>                Requires<[IsISA3_0]>;
> Here I am not able to understand against which DAG pattern this gets 
> matched ? By doing grep I don't get any code which provide me the 
> required info.
I don't think we have a pattern for that instruction currently. We have 
a CMPB instruction, which we can automatically generate, and sounds 
similar to your desired semantics, see PPCDAGToDAGISel::combineToCMPB in 
PPCISelDAGToDAG.cpp.

  -Hal
>
> Basically I want to know which LLVM IR instruction or intrinsic has 
> similar semantics and then how I can lower it correctly.
>
> Sincerely,
> Vivek
>
>
>
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
-- 
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory

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