llvm dev - Feb 2017 - x86 and GPU backend support for irregular accesses

Hello !

Does the x86 back-end generate gather-scatter instructions for
LLVM gather-scatter intrinsics ?

Also, do the NVPTX and AMDGPU back-ends generate equivalent instructions
for GPUs ?

Thank You,
Sanjay
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On Mon, Feb 20, 2017, at 05:19 PM, SANJAY SRIVALLABH SINGAPURAM via
llvm-dev wrote:
> Hello !
> 
> Does the x86 back-end generate gather-scatter instructions for
> LLVM gather-scatter intrinsics ?
> 
> Also, do the NVPTX and AMDGPU back-ends generate equivalent instructions
> for GPUs ?
Dear Sanjay,

I suggest to just try this out. Create a simple test case and see what
kind of assembly code is generated. Interesting will certainly be the
AVX512 instructions for Xeon PHI.

Best,
Tobias
> 
> Thank You,
> Sanjay
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

What do you expect by meaning "equivalent" instructions in NVPTX
backend?

On Feb 20, 2017 9:56 PM, "Tobias Grosser via llvm-dev" <
llvm-dev at lists.llvm.org> wrote:
> On Mon, Feb 20, 2017, at 05:19 PM, SANJAY SRIVALLABH SINGAPURAM via
> llvm-dev wrote:
> > Hello !
> >
> > Does the x86 back-end generate gather-scatter instructions for
> > LLVM gather-scatter intrinsics ?
> >
> > Also, do the NVPTX and AMDGPU back-ends generate equivalent
instructions
> > for GPUs ?
>
> Dear Sanjay,
>
> I suggest to just try this out. Create a simple test case and see what
> kind of assembly code is generated. Interesting will certainly be the
> AVX512 instructions for Xeon PHI.
>
> Best,
> Tobias
>
> >
> > Thank You,
> > Sanjay
> > _______________________________________________
> > LLVM Developers mailing list
> > llvm-dev at lists.llvm.org
> > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
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Hello Madhur,

I meant any instructions that enable irregular accesses at the hardware
level, e.g. a subset of Intel's AVX 512 and those here
<https://software.intel.com/en-us/articles/understanding-gather-scatter-instructions-and-the-gather-scatter-unroll-compiler-switch>
.

Thanks,
Sanjay

On Mon, Feb 20, 2017 at 9:49 PM SANJAY SRIVALLABH SINGAPURAM <
llvmresch_int01 at iith.ac.in> wrote:
> Hello !
>
> Does the x86 back-end generate gather-scatter instructions for
> LLVM gather-scatter intrinsics ?
>
> Also, do the NVPTX and AMDGPU back-ends generate equivalent instructions
> for GPUs ?
>
> Thank You,
> Sanjay
>
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