vivek pandya via llvm-dev
2017-Feb-23 10:22 UTC
[llvm-dev] Help required, Target Specifc SDNode getting optimized by ISel DAG
Hi Krzysztof, Thanks for reply, I checked that and it seems to be ok. How ever I noticed that my build is have this problem on other architectures too. Only x86 is generating return instruction. Also epilogue loads are also missing. I think I have done some thing wrong to some target independent code. -Vivek> > > Hi Vivek, > Make sure that you return the correct chain from LowerReturn. > > -Krzysztof > > > On 2/22/2017 7:17 AM, vivek pandya via llvm-dev wrote: > > Hello LLVM Devs, > > > > I am trying to compile following simple program for an experimental > backend > > > > int main() > > { > > printf("Hello World \n"); > > return 0; > > } > > > > I have added code to lower return instruction in the backend however in > > assembly I don't find return instruction generated. > > In the debug-only=isel dump I can see that my target specific SDNode for > > RET_FLAG is added but it gets removed during DAG > > optimization phase. > > > > > > Initial selection DAG: BB#0 'main:entry' > > SelectionDAG has 18 nodes: > > t5: i32 = GlobalAddress<i32 (i8*, ...)* @printf> 0 > > t0: ch = EntryToken > > t4: ch = store<ST4[%retval]> t0, Constant:i32<0>, > > FrameIndex:i32<0>, undef:i32 > > t8: ch,glue = callseq_start t4, TargetConstant:i32<0> > > > > t10: ch,glue = CopyToReg t8, Register:i32 %R5, GlobalAddress:i32<[14 x > > i8]* @.str> 0 > > t12: ch,glue = DummyArchISD::CALL t10, TargetGlobalAddress:i32<i32 > > (i8*, ...)* @printf> 0, Register:i32 %R5, t10:1 > > t13: ch,glue = callseq_end t12, TargetConstant:i32<0>, > > TargetConstant:i32<0>, t12:1 > > t15: i32,ch,glue = CopyFromReg t13, Register:i32 %R3, t13:1 > > > > t16: ch,glue = CopyToReg t15:1, Register:i32 %R3, Constant:i32<0> > > > > t17: ch = DummyArchISD::RET_FLAG t16, Register:i32 %R3, t16:1 > > > > t15: i32,ch,glue = CopyFromReg t13, Register:i32 %R3, t13:1 > > > > > > Optimized lowered selection DAG: BB#0 'main:entry' > > SelectionDAG has 15 nodes: > > t0: ch = EntryToken > > t4: ch = store<ST4[%retval]> t0, Constant:i32<0>, > > FrameIndex:i32<0>, undef:i32 > > t8: ch,glue = callseq_start t4, TargetConstant:i32<0> > > > > t10: ch,glue = CopyToReg t8, Register:i32 %R5, GlobalAddress:i32<[14 x > > i8]* @.str> 0 > > t12: ch,glue = DummyArchISD::CALL t10, TargetGlobalAddress:i32<i32 > > (i8*, ...)* @printf> 0, Register:i32 %R5, t10:1 > > t13: ch,glue = callseq_end t12, TargetConstant:i32<0>, > > TargetConstant:i32<0>, t12:1 > > t15: i32,ch,glue = CopyFromReg t13, Register:i32 %R3, t13:1 > > > > > > > > Can someone please guide me how to furhter debug this situation? Or any > > hints. > > > > Sincerely, > > Vivek > > > > > > _______________________________________________ > > LLVM Developers mailing list > > llvm-dev at lists.llvm.org > > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > > > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > hosted by The Linux Foundation > > >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170223/c33939fa/attachment.html>