search for: immsext16

I am working on an experimental target and trying to make sure that the load offset field is used to the best way. There appears to be some control over the architecture's offset range and whether the offset is too large and needs to be lowered/converted into a separate sequence of operations in DAGSelection? Can someone point me to what might be the case? For example, the difference between

...mplicit register output if there are no outputs given to the pattern? I'm also curious about how did LLVM know that an output of this instruction was setting a flag in a special purpose register rather than a GPR? When I look at the DAG pattern for the instruction, (Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond), I can't find anything saying that it sets a flag in the special purpose register. I'm reposting code for convenience. def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; def Escalatflag : SDNode<"EscalaISD::SET_FLAG", SDT_Esca...

...", SDT_EsenciaSetFlag, [SDNPOutGlue]>; class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm), !strconcat(asmstr, "i\t$rA, $imm"), [(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> { bits<5> op2; bits<5> rA; bits<16> imm; let Inst{25-21} = op2; let Inst{20-16} = rA; let Inst{15-0} = imm; let format = AFrm; let op2 = op2Val; } -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part --------------...

..., [{return (N->getZExtValue() == ISD::SETLT);}]>; class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm), !strconcat(asmstr, "i\t$rA, $imm"), [(Esenciasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> { bits<5> op2; bits<5> rA; bits<16> imm; let Inst{25-21} = op2; let Inst{20-16} = rA; let Inst{15-0} = imm; let format = AFrm; let op2 = op2Val; } defm SFLTS : SF<0xc, "l.sflts", Esencia_CC_LT>; ========================= Modifie...

if I write: int z, x; ... z = (x >= k); -- where k is a constant The compiler always wants to translate this into: z = (x > (k-1)); In general this can often lead to better code (and it does for Mips 16 for sure), except at the boundary condition where k==-32768 Then it creates the literal -32769 which cannot be placed in a simple immediate field. That creates a lot of extra code for

Hi Johnny, Thank you for your help. I guess the pseudo instruction does not interfere in the generated assembly code. I'll check the file that describes the registers and I hope understand why the assembly code is printed wrong (now is printed things like add r1, r0, -40). Cheers, Carlos Carlos Almeida Jr On Thu, Nov 27, 2014 at 7:56 AM, Johnny Val <johnnydval at gmail.com> wrote:

...", - [(PPCcmp_unres G8RC:$rA, G8RC:$rB, imm:$label)]>; -def CMP_UNRESdi : Pseudo<(outs), (ins G8RC:$rA, s16imm64:$imm, i32imm:$label), - "cmpdi $rA, $imm\n\tbne- La${label}_exit", - [(PPCcmp_unres G8RC:$rA, immSExt16:$imm, imm:$label)]>; -} +let Defs = [CR0] in +def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), + "stdcx. $rS, $dst", LdStSTDCX, + [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, + isDOT; let isCall = 1, isTerminator = 1...

...atterns from the MipsInstrInfo.td //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// // Small immediates def : MipsPat<(i32 immSExt16:$in), (ADDiu ZERO, imm:$in)>; def : MipsPat<(i32 immZExt16:$in), (ORi ZERO, imm:$in)>; def : MipsPat<(i32 immLow16Zero:$in), (LUi (HI16 imm:$in))>; Here are some which have several instructions multiclass SetgePats<RegisterClass RC, I...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...", - [(PPCcmp_unres G8RC:$rA, G8RC:$rB, imm:$label)]>; -def CMP_UNRESdi : Pseudo<(outs), (ins G8RC:$rA, s16imm64:$imm, i32imm:$label), - "cmpdi $rA, $imm\n\tbne- La${label}_exit", - [(PPCcmp_unres G8RC:$rA, immSExt16:$imm, imm:$label)]>; -} +let Defs = [CR0] in +def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), + "stdcx. $rS, $dst", LdStSTDCX, + [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, + isDOT; let isCall = 1, isTerminator = 1...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...", - [(PPCcmp_unres G8RC:$rA, G8RC:$rB, imm:$label)]>; -def CMP_UNRESdi : Pseudo<(outs), (ins G8RC:$rA, s16imm64:$imm, i32imm:$label), - "cmpdi $rA, $imm\n\tbne- La${label}_exit", - [(PPCcmp_unres G8RC:$rA, immSExt16:$imm, imm:$label)]>; -} +let Defs = [CR0] in +def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), + "stdcx. $rS, $dst", LdStSTDCX, + [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, + isDOT; let isCall = 1, isTerminator = 1...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...", - [(PPCcmp_unres G8RC:$rA, G8RC:$rB, imm:$label)]>; -def CMP_UNRESdi : Pseudo<(outs), (ins G8RC:$rA, s16imm64:$imm, i32imm:$label), - "cmpdi $rA, $imm\n\tbne- La${label}_exit", - [(PPCcmp_unres G8RC:$rA, immSExt16:$imm, imm:$label)]>; -} +let Defs = [CR0] in +def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), + "stdcx. $rS, $dst", LdStSTDCX, + [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, + isDOT; let isCall = 1, isTerminator = 1...

Thanks for your reply. We are trying to implement a simple Mips-based CPU with just for teaching purpose, so we delete some instructions which are not commonly used, thus the task won't be too hard for students. I am responsible for modifying the compiler so that the compiler won't emit unsupported instructions. In order to avoid "can not select" error, I am trying to expand

...the Mips Target as a base. Coming along quite well, currently ran into two problems with my sample/test program. The main issue I am having is with respect to the following (Note: I have already changed ADDui from ADDiu) We have this def ADDui : ArithI<0x09, "addui", add, simm16, immSExt16>; However sticky speaking this should be in dlx the instructions are addui rk, ri, Kuns (Where Kusn is unsigned) Likewise DLX has a subui rk, ri, Kusn. (Mips does not) Thus they should be: def ADDui : ArithI<0x09, "addui", add, simm16, immZExt16>; def SUBui : ArithI<0x2...