Displaying 7 results from an estimated 7 matches for "sdt_escalasetflag".
2016 Feb 02
2
New register class and patterns
...rn. i32:$sA should work etc.
>
> -Matt
>
> Let me clarify.
>
> I'm not sure I understand what you are saying. Let me post more information.
>
> Here is what I have defined for Escalasetflag
>
> def Escalasetflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag,
> [SDNPOutGlue]>;
>
> How come it was working before and is is not working now? Clearly I'm missing something, but I can't figure out what.
>
> Any help is appreciated.
>
>
> --
> Rail Shafigulin
> Software Engineer
> E...
2016 Feb 03
2
New register class and patterns
....com>
wrote:
>
> Let me clarify.
>>
>> I'm not sure I understand what you are saying. Let me post more
>> information.
>>
>> Here is what I have defined for Escalasetflag
>>
>> def Escalasetflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag,
>> [SDNPOutGlue]>;
>>
>> How come it was working before and is is not working now? Clearly I'm
>> missing something, but I can't figure out what.
>>
>> Any help is appreciated.
>>
>>
>> --
>> Rail S...
2016 Feb 04
2
New register class and patterns
...ot have an output register. It sets a flag in
the special purpose register. So why creating a new register class would
cause a problem? In other words, since there is no output register, why
would LLVM start complaining. Below I'm repeating some code for reference.
Any help is appreciated.
def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag,
[SDNPOutGlue]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (i...
2016 Feb 03
2
New register class and patterns
On Tue, Feb 2, 2016 at 8:42 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>
> On Feb 2, 2016, at 16:52, Rail Shafigulin <rail at esenciatech.com> wrote:
>
> def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
>
>
> I think for setting an implicit register, you still need to have 1 result
> here.
>
> If you look at SDTX86CmpPTest, I think this is similar to what you are
> trying to do.
>
> -Matt
>
def SDTX86CmpPT...
2016 Jan 30
1
New register class and patterns
> On Jan 29, 2016, at 13:25, Rail Shafigulin via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
>
>
> I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details:
>
> defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
>
> multiclass SF<bits<5> op2Val, string asmstr, PatLeaf
2016 Feb 04
2
New register class and patterns
...etting a flag in a
special purpose register rather than a GPR? When I look at the DAG pattern
for the instruction, (Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond), I
can't find anything saying that it sets a flag in the special purpose
register.
I'm reposting code for convenience.
def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
def Escalatflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag,
[SDNPOutGlue]>;
def Escala_CC_EQ : PatLeaf<(imm),
[{return (N->getZExtValue() == ISD::SETEQ);}...
2016 Jan 29
3
New register class and patterns
On Fri, Jan 29, 2016 at 10:22 AM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 1/28/2016 8:11 PM, Rail Shafigulin via llvm-dev wrote:
>
>>
>> Would anyone be able to figure out why this is happening? I can provide
>> more code if needed.
>>
>
> The error message should show what types have been inferred so far.
>
> You